High -level synthesis for dynamically reconfigurable systems - Zhang, Xue-jie (ProQuest Dissertations & Theses, 2000)
We present in this thesis a high-level synthesis technique for dynamically reconfigurable systems. For a dynamically reconfigurable design, conventional synthesis techniques will not be able to enforce dynamic reconfigurations because these techniques are targeted at a static circuit of fixed size and functionality. In order to generate an efficient dynamically reconfigurable design, we propose a new high-level synthesis methodology that considers the reconfigurability of the high-level system specifications. The synthesis methodology is subdivided into the following steps: Firstly, we model the specification in a combined formalism called the extended control data flow graph, that combines the advantages of both graph-based and algebra-based approaches, such that the temporal nature of a system can be abstracted, analyzed and synthesized. Secondly, we present an analysis technique where the dynamically reconfigurable system is analyzed, and dynamic reconfiguration constraints such as configuration granularity, functional locality of the system and reconfiguration overhead are quantified. In order to produce an usable framework for the high-level synthesis of a dynamically reconfigurable design, we present two techniques for solving the high-level synthesis problem for dynamically reconfigurable systems. First, we present a configuration bundling technique subject to trade-offs between maximizing resource usage and minimizing reconfiguration overhead in space. Then, we present a technique for synthesizing the reconfigurations of the design by configuration bundling driven module allocation and temporal partitioning with scheduling. These techniques can be used to obtain a dynamically reconfigurable design that optimizes the design goal globally while satisfying the dynamic resource constraints. Finally, we solve the high-level synthesis problems through a genetic algorithm, which performs temporal partitioning, resource allocation and scheduling simultaneously for meeting design constraints, maximizing resource usage and minimizing reconfiguration overhead.