Characterization, modeling, and design of ESD protection circuits
For more than 20 years, susceptibility of integrated circuits to electrostatic discharge (ESD) has warranted the use of dedicated on-chip ESD protection circuits. In the past, increased sensitivity of smaller devices, coupled with a lack of understanding of ESD phenomena and the consequent trial-and...
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| Format: | Dissertation |
| Language: | English |
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ProQuest Dissertations & Theses
01.01.1998
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| ISBN: | 0591908662, 9780591908664 |
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| Abstract | For more than 20 years, susceptibility of integrated circuits to electrostatic discharge (ESD) has warranted the use of dedicated on-chip ESD protection circuits. In the past, increased sensitivity of smaller devices, coupled with a lack of understanding of ESD phenomena and the consequent trial-and-error approach to ESD circuit design, resulted in design of ESD protection effectively starting from scratch in each new technology. Now, as life cycles of new technologies continue to decrease, better analysis capabilities and a systematic design approach are essential to accomplishing the increasingly difficult task of adequate ESD protection-circuit design. This thesis reviews the problems of ESD in the integrated circuit (IC) industry and the standard models used to characterize ESD protection-circuit performance. Previous approaches to ESD circuit design are discussed, including design theory and specific design examples. Transmission-line pulsing (TLP), a relatively new ESD characterization and analysis test method, is presented. Dependences of ESD circuit performance on critical process parameters of a CMOS technology are discussed. Two-dimensional numerical device simulation techniques are presented for modeling ESD in circuits, including electrothermal simulation and a curve-tracing algorithm, detailed in an appendix, used to guide simulations through complex current-voltage (I-V) curves. Results are given for TLP experiments run on parametric ESD structures created in a 0.5$\mu$m CMOS technology, including MOSFET snapback I-V characteristics and failure thresholds. Results of calibrated simulations are also presented and compared to experiments. Details of the simulation calibration procedure are provided. A design methodology for multiple-fingered CMOS ESD protection transistors is presented. The methodology employs empirical modeling to predict the I-V characteristics and ESD withstand level of a circuit given the circuit's layout parameters. A critical correlation between transmission-line pulse withstand current and human-body model (HBM) withstand voltage is demonstrated. Quantitative prediction is achieved for HBM withstand voltages in a 0.35$\mu$m-technology SRAM circuit. Optimization of protection-transistor layout area for a given ESD withstand level is illustrated. |
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| AbstractList | For more than 20 years, susceptibility of integrated circuits to electrostatic discharge (ESD) has warranted the use of dedicated on-chip ESD protection circuits. In the past, increased sensitivity of smaller devices, coupled with a lack of understanding of ESD phenomena and the consequent trial-and-error approach to ESD circuit design, resulted in design of ESD protection effectively starting from scratch in each new technology. Now, as life cycles of new technologies continue to decrease, better analysis capabilities and a systematic design approach are essential to accomplishing the increasingly difficult task of adequate ESD protection-circuit design. This thesis reviews the problems of ESD in the integrated circuit (IC) industry and the standard models used to characterize ESD protection-circuit performance. Previous approaches to ESD circuit design are discussed, including design theory and specific design examples. Transmission-line pulsing (TLP), a relatively new ESD characterization and analysis test method, is presented. Dependences of ESD circuit performance on critical process parameters of a CMOS technology are discussed. Two-dimensional numerical device simulation techniques are presented for modeling ESD in circuits, including electrothermal simulation and a curve-tracing algorithm, detailed in an appendix, used to guide simulations through complex current-voltage (I-V) curves. Results are given for TLP experiments run on parametric ESD structures created in a 0.5$\mu$m CMOS technology, including MOSFET snapback I-V characteristics and failure thresholds. Results of calibrated simulations are also presented and compared to experiments. Details of the simulation calibration procedure are provided. A design methodology for multiple-fingered CMOS ESD protection transistors is presented. The methodology employs empirical modeling to predict the I-V characteristics and ESD withstand level of a circuit given the circuit's layout parameters. A critical correlation between transmission-line pulse withstand current and human-body model (HBM) withstand voltage is demonstrated. Quantitative prediction is achieved for HBM withstand voltages in a 0.35$\mu$m-technology SRAM circuit. Optimization of protection-transistor layout area for a given ESD withstand level is illustrated. |
| Author | Beebe, Stephen Glen |
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