Reconciling performance and predictability on a many-core through off-line mapping

We start from a general-purpose many-core architecture designed for average-case performance and ease of use. In particular, its distributed shared memory programming model allows the use of a code generation flow based on the (unmodified) gcc compiler chain. We modify this architecture and extend t...

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Bibliographic Details

Published in:	2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC) pp. 1 - 8
Main Authors:	Carle, Thomas, Djemal, Manel, Genius, Daniela, Pecheux, Francois, Potop Butucaru, Dumitru, de Simone, Robert, Wajsburt, Franck, Zhen Zhang
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.05.2014
Subjects:	Computer architecture Hardware Processor scheduling Random access memory Real-time systems Scheduling Timing
Online Access:	Get full text
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