Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementation

Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level adequation algorithm architecture process. We present a method generates automatic...

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Vydáno v:IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06) s. 2 pp.
Hlavní autoři: Berthelot, F., Nouvel, F.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.06.2006
Témata:
Design methodology
Digital signal processors
Field programmable gate arrays
Hardware
Multimedia systems
Runtime
Signal processing algorithms
Software performance
Software radio
Switches
ISBN:0769525334, 9780769525334
ISSN:2159-3469
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Shrnutí:Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level adequation algorithm architecture process. We present a method generates automatically the design for both partially and fixed parts of FPGAs
ISBN:0769525334
9780769525334
ISSN:2159-3469
DOI:10.1109/ISVLSI.2006.71