Performance of FPGA-Based Implementations of Data Classification Techniques Using HDL Coder - Zafar, Adil (ProQuest Dissertations & Theses, 2022)
In the modern age, data is being generated at a massive rate and this data can be analyzed and utilized in many applications such as image recognition, speech recognition, behavioral analysis and so on. Therefore, data classification techniques have become very important. Many data classification techniques require high computation power and one way to reach high computation power is through parallelization. Field programmable gate arrays (FPGA) are good platforms for parallel computation in real time. However, FPGAs can only be configured through Hardware description languages (HDL) which can become tedious and complicated when trying to implement complex algorithms. To circumvent this issue, High-level synthesis (HLS) tools have been developed. These allow engineers to code their design in high-level languages such as C/C++ and the HLS tools help convert the program into FPGA synthesizable code. One of these tools is the HDL Coder by The MathWorks Inc. The HDL Coder can be used in the MATLAB scripts or the Simulink environment. Both these platforms are relatively easier to use as compared to other programming languages. And the HDL Coder can convert a script or Simulink model into an HDL. Therefore, the purpose of this thesis is to implement data classification techniques using Simulink with HDL Coder onto a Basys 3 FPGA board. Using a scalable and modular approach, three different algorithms are implemented in this thesis with varying parameters, and their resource utilization is recorded. The three algorithms are the fast Fourier transform (FFT), the discrete cosine transform (DCT), and the K-Nearest Neighbor (KNN) algorithm. The accessibility of the HDL coder was also accounted for by documenting the procedure for the implementation.