Source-Level Debugging for Hardware Generator Frameworks - Zhang, Keyi (ProQuest Dissertations & Theses, 2022)
Historically, hardware was specified manually in hardware description languages (HDLs) such as SystemVerilog and VHSIC Hardware Description Language (VHDL). Although these languages have evolved over the years, it is increasingly difficult for them to keep up with the trend of hardware customization and specialization, where a family of hardware is created with minor variants for different use cases. The parameterization and template language features offered in these HDLs can no longer satisfy the complex nature of hardware design, increasing the engineering cost [2]. In response to this problem, Ofer Shacham et al. [3] argued that we should rethink the traditional hardware design: instead of building a new customized chip for every application, we should reuse the design process to generate multiple new chips, which is done through a set of frameworks called hardware generators.Following the new design paradigm shift, designers have seen various hardware generator frameworks developed and used in practice over the past decade. Many frameworks are embedded into other high-level programming languages, i.e., embedded domain-specific languages (eDSL), such as magma [4] (Python) and Chisel [5] (Scala). This kind of framework requires designers to write a program in the eDSL, which later is executed or compiled to produce Register-Transfer Level (RTL). In these systems, the designers usually need to fully specify the cycle-level timing behavior of the hardware in the eDSL. This constraint is relaxed in High-Level Synthesis (HLS), another form of hardware generator, where designers specify only the high-level logic and scheduling directives: the compiler is responsible for producing a valid schedule given timing and resource constraints.Unfortunately, however, many features introduced in the frameworks to increase design productivity and synthesis quality make the generated RTL difficult for the designers to read and to understand. This is because the compiler transformations and optimizations often obfuscate the code. Since most intellectual property (IP) blocks are transferred at the RTL level, electronic design automation (EDA) engineers focus on optimizing RTL-level simulation and verification. As a result, any system-level verification has to be done at the RTL level, and hardware designers have to debug the system-level issues with RTL, which contains the generated code. Consequently, this generated code makes the generator frameworks difficult to debug [6, 7, 8].While it might be tempting to fix the debugging problem by removing hardware generators–after all, more time is spent on validation than design [9]–this would be a bad decision. In many eDSLfocused generator frameworks, the designer can use many host language features, such as objectoriented programming, functional programming, and complex data types, which offer stronger type safety guarantee. Because program execution involves many sequential stages, designers can instead use software languages to control the hardware generation process. These software programming techniques overcome the limitations of traditional HDLs and improve design productivity [5, 10, 6, 11].To continue to leverage these advantages, the work presented in this thesis demonstrates how we can apply source-level software debugging techniques to create a powerful debugging system for hardware generators. Software debugging systems are extremely useful for this purpose because they deal with problems in software similar to that discussed above, namely, when the execution environment, such as CPU or virtual machine instructions, is drastically different from the source code.