Design and Optimization of LLVM Compiler for Domestic High Performance Accelerator

National University of Defense Technology independently developed a high-performance accelerator that uses an on-chip heterogeneous fusion architecture of a Central Processing Unit(CPU) and General Purpose Digital Signal Processor(GPDSP). The GPDSP,with its Very Long Instruction Word(VLIW)+ Single I...

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Vydané v:Ji suan ji gong cheng Ročník 50; číslo 4; s. 321 - 331
Hlavný autor: SONG Qiang, TANG Junlong, CHEN Zhaoyun, SHI Yang, TAN Qixuan, XIAO Ziyang, ZOU Wanghui
Médium: Journal Article
Jazyk:Chinese
English
Vydavateľské údaje: Editorial Office of Computer Engineering 15.04.2024
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general purpose digital signal processor(gpdsp)|low level virtual machine(llvm)|compiler|instruction scheduling|vector instruction interface
ISSN:1000-3428
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Abstract National University of Defense Technology independently developed a high-performance accelerator that uses an on-chip heterogeneous fusion architecture of a Central Processing Unit(CPU) and General Purpose Digital Signal Processor(GPDSP). The GPDSP,with its Very Long Instruction Word(VLIW)+ Single Instruction Multiple Datastream(SIMD) vectorization structure,is the main support for the peak performance acceleration core. However,mainstream compilers cannot adequately support high-performance accelerators in intensive data calculation instruction layouts,static allocation of hardware execution units for instructions,and GPDSP-specific vector instructions. In this study,based on the Low Level Virtual Machine(LLVM) compilation framework,the PERP method,Ant Colony Optimization(ACO) algorithm,and GPDSP structural characteristics are combined to optimize the cost model in the pre-RA-sched stage,and the instruction scheduling module is designed to support register pressure awareness. This study proposes an instruction scheduling strategy that supports static functional unit allocation in the post-RA-sched stage,which guarantees correct functional unit allocation through a conflict detection mechanism,and provides a software basis for the parallel execution of instructions. Furthermore,a series of rich and regular vector instruction interfaces are encapsulated in the backend to support the GPDSP vector instructions. The experimental results demonstrate that the LLVM compilation architecture optimization method proposed in this study provides good support for the GPDSP in terms of both functionality and performance. Specifically,the overall performance average speedup ratio of GCC testsuite is 4.539,the overall performance average speedup ratio of SPEC CPU 2017 floating-point test is 4.49,and the overall performance average speedup ratio of SPEC CPU 2017 integer test is 3.24. Additionally,the vector program using vector interfaces achieves an average performance improvement ratio of 97.1%.
AbstractList National University of Defense Technology independently developed a high-performance accelerator that uses an on-chip heterogeneous fusion architecture of a Central Processing Unit(CPU) and General Purpose Digital Signal Processor(GPDSP). The GPDSP,with its Very Long Instruction Word(VLIW)+ Single Instruction Multiple Datastream(SIMD) vectorization structure,is the main support for the peak performance acceleration core. However,mainstream compilers cannot adequately support high-performance accelerators in intensive data calculation instruction layouts,static allocation of hardware execution units for instructions,and GPDSP-specific vector instructions. In this study,based on the Low Level Virtual Machine(LLVM) compilation framework,the PERP method,Ant Colony Optimization(ACO) algorithm,and GPDSP structural characteristics are combined to optimize the cost model in the pre-RA-sched stage,and the instruction scheduling module is designed to support register pressure awareness. This study proposes an instruction scheduling strategy that supports static functional unit allocation in the post-RA-sched stage,which guarantees correct functional unit allocation through a conflict detection mechanism,and provides a software basis for the parallel execution of instructions. Furthermore,a series of rich and regular vector instruction interfaces are encapsulated in the backend to support the GPDSP vector instructions. The experimental results demonstrate that the LLVM compilation architecture optimization method proposed in this study provides good support for the GPDSP in terms of both functionality and performance. Specifically,the overall performance average speedup ratio of GCC testsuite is 4.539,the overall performance average speedup ratio of SPEC CPU 2017 floating-point test is 4.49,and the overall performance average speedup ratio of SPEC CPU 2017 integer test is 3.24. Additionally,the vector program using vector interfaces achieves an average performance improvement ratio of 97.1%.
Author SONG Qiang, TANG Junlong, CHEN Zhaoyun, SHI Yang, TAN Qixuan, XIAO Ziyang, ZOU Wanghui
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  fullname: SONG Qiang, TANG Junlong, CHEN Zhaoyun, SHI Yang, TAN Qixuan, XIAO Ziyang, ZOU Wanghui
  organization: 1. School of Physical and Electronic Sciences, Changsha University of Science and Technology, Changsha 410114, Hunan, China;2. School of Computer, National University of Defense Technology, Changsha 410073, Hunan, China
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SubjectTerms general purpose digital signal processor(gpdsp)|low level virtual machine(llvm)|compiler|instruction scheduling|vector instruction interface
Title Design and Optimization of LLVM Compiler for Domestic High Performance Accelerator
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