Design and VLSI Implementation of Multilayered Neural Network Architecture Using Parallel Processing and Pipelining Algorithm for Image Compression

In this paper, an optimized high speed parallel processing architecture with pipelining for multilayer neural network for image compression and decompression is implemented on FPGA (Field-Programmable Gate Array). The multilayered feed forward neural network architecture is trained using 20 sets of...

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Veröffentlicht in:	I-Manager's Journal on Software Engineering Jg. 8; H. 3; S. 13 - 25
Hauptverfasser:	Mohan, Murali, ., Sathyanarayana
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Nagercoil iManager Publications 01.01.2014
Schlagworte:	Algorithms Architecture Architecture (computers) Computer simulation Data compression Field programmable gate arrays High speed machining Image compression Image processing systems Neural networks Parallel processing Programming
ISSN:	0973-5151, 2230-7168
Online-Zugang:	Volltext
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