Design and VLSI Implementation of Multilayered Neural Network Architecture Using Parallel Processing and Pipelining Algorithm for Image Compression

In this paper, an optimized high speed parallel processing architecture with pipelining for multilayer neural network for image compression and decompression is implemented on FPGA (Field-Programmable Gate Array). The multilayered feed forward neural network architecture is trained using 20 sets of...

Full description

Bibliographic Details

Published in:	I-Manager's Journal on Software Engineering Vol. 8; no. 3; pp. 13 - 25
Main Authors:	Mohan, Murali, ., Sathyanarayana
Format:	Journal Article
Language:	English
Published:	Nagercoil iManager Publications 01.01.2014
Subjects:	Algorithms Architecture Architecture (computers) Computer simulation Data compression Field programmable gate arrays High speed machining Image compression Image processing systems Neural networks Parallel processing Programming
ISSN:	0973-5151, 2230-7168
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!