Design and VLSI Implementation of Multilayered Neural Network Architecture Using Parallel Processing and Pipelining Algorithm for Image Compression
In this paper, an optimized high speed parallel processing architecture with pipelining for multilayer neural network for image compression and decompression is implemented on FPGA (Field-Programmable Gate Array). The multilayered feed forward neural network architecture is trained using 20 sets of...
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| Veröffentlicht in: | I-Manager's Journal on Software Engineering Jg. 8; H. 3; S. 13 - 25 |
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iManager Publications
01.01.2014
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| ISSN: | 0973-5151, 2230-7168 |
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| Abstract | In this paper, an optimized high speed parallel processing architecture with pipelining for multilayer neural network for image compression and decompression is implemented on FPGA (Field-Programmable Gate Array). The multilayered feed forward neural network architecture is trained using 20 sets of image data based to obtain the appropriate weights and biases that are used to construct the proposed architecture. Verilog code developed is simulated using ModelSim for verification. The FPGA implementation is carried out using Xilinx ISE 10.1. The implementation is performed on Virtex-5 FPGA board. Once interfacing is done, the corresponding programming file for the top module is generated. The target device is then configured, programming file is generated and can be successfully dumped on Virtex-5. The design is then analyzed using Chip Scope Pro. The Chip Scope output is observed. The output is successfully compared with VCS (Verliog Compiler Simulator) simulation output. The design is optimized for power of 1.01485 W and memory of 540916 KB. |
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| AbstractList | In this paper, an optimized high speed parallel processing architecture with pipelining for multilayer neural network for image compression and decompression is implemented on FPGA (Field-Programmable Gate Array). The multilayered feed forward neural network architecture is trained using 20 sets of image data based to obtain the appropriate weights and biases that are used to construct the proposed architecture. Verilog code developed is simulated using ModelSim for verification. The FPGA implementation is carried out using Xilinx ISE 10.1. The implementation is performed on Virtex-5 FPGA board. Once interfacing is done, the corresponding programming file for the top module is generated. The target device is then configured, programming file is generated and can be successfully dumped on Virtex-5. The design is then analyzed using Chip Scope Pro. The Chip Scope output is observed. The output is successfully compared with VCS (Verliog Compiler Simulator) simulation output. The design is optimized for power of 1.01485 W and memory of 540916 KB. |
| Author | Sathyanarayana Mohan, Murali |
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| Cites_doi | 10.1016/S0923-5965(98)00041-1 10.1049/el:19930403 10.1109/nnsp.1991.239492 10.1016/s0262-8856(01)00042-7 10.1016/s0377-2217(97)00370-6 10.1016/s0923-5965(98)00041-1 10.1016/s0952-1976(98)00056-6 10.1109/5.364461 10.1109/7.481272 10.1109/IJCNN.1989.118675 10.1109/icassp.1991.150989 10.1049/el:19900310 10.1080/0232929032000115182 |
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| CorporateAuthor | Associate Professor, Department of ECE, Sri Venkateswara College of Engineering and Technology, Chittoor, A.P, India Professor, Department of ECE, College of Engineering, S.V. University, Tirupati, A.P, India |
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| DOI | 10.26634/jse.8.3.2808 |
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| References_xml | – year: 2005 ident: ref4 article-title: Image Compression Using Neural Networks, Image Processing and Machine Vision Conference (MVIP) – volume: 8 start-page: 846 volume-title: Proc 43rd IEEE Mdwest Symp on Circuits and Systems year: 2001 ident: ref3 article-title: Neural Networks-based Image Compression System – start-page: 1228 volume-title: IEEE Workshop on Neural Networks for Signal Processing year: 1992 ident: ref9 article-title: Compression of subband-filterd images via neural networks – volume: 14 start-page: 737 issn: 09235965 year: 1999 ident: ref2 article-title: Image Compression with Neural Networks - A Survey publication-title: Signal Process Image Commun doi: 10.1016/S0923-5965(98)00041-1 – volume: 29 start-page: 127 issn: 00135194 issue: No 7 year: 1993 ident: ref10 article-title: Image compression by edge pattern learning using multilayer perceptron publication-title: Electron Lett doi: 10.1049/el:19930403 – start-page: 58 volume-title: IEEE Workshop on Neural Networks for Signal Processing year: 1991 ident: ref8 article-title: Improved structures based on neural networks for image compression doi: 10.1109/nnsp.1991.239492 – volume: 19 start-page: 245 issn: 02628856 issue: No.9 year: 2001 ident: ref19 article-title: Image compression using principal component neural networks publication-title: Image Vis Comput doi: 10.1016/s0262-8856(01)00042-7 – volume: 108 start-page: 354 issn: 03772217 issue: No.12 year: 1998 ident: ref13 article-title: Neural networks for image and video compression: A review publication-title: Eur J Oper Res doi: 10.1016/s0377-2217(97)00370-6 – volume: 14 start-page: 713 issue: No. 9 year: 1999 ident: ref12 article-title: Image compression with neural networks -A survey publication-title: Image Communication ELSEVIER doi: 10.1016/s0923-5965(98)00041-1 – volume: 12 start-page: 210 issn: 09521976 issue: No.5 year: 1999 ident: ref16 article-title: A competitive continuous Hopfield neural network for vector quantization in image compression publication-title: Eng Appl Artif Intell doi: 10.1016/s0952-1976(98)00056-6 – volume: 83 start-page: 288 issn: 00189219 issue: No. 2 year: 1995 ident: ref0 article-title: Neural Network Approaches to Image Compression publication-title: Proc IEEE doi: 10.1109/5.364461 – volume: 32 start-page: 189 issn: 00189251 issue: No.1 year: 1996 ident: ref15 article-title: Image compression with a hierarchical neural network publication-title: IEEE Trans Aerosp Electron Syst doi: 10.1109/7.481272 – volume: 8 start-page: 288 volume-title: International Joint Conference on Neural Networks year: 1989 ident: ref5 article-title: Image compression using a neural network model doi: 10.1109/IJCNN.1989.118675 – start-page: 95 volume-title: 48th International Symposium ELMAR-2006 year: 2006 ident: ref1 article-title: An Experience in Image Compression Using Neural Networks – start-page: 156 volume-title: Proceeding of International Conference on Acoustic Speech and Signal Processing year: 1991 ident: ref7 article-title: Improved neural structure for image compression doi: 10.1109/icassp.1991.150989 – volume: 26 start-page: 477 issn: 00135194 year: 1990 ident: ref6 article-title: Artificial neural network for image compression publication-title: Electron Lett doi: 10.1049/el:19900310 – year: 2001 ident: ref17 article-title: A Vector Quantization – Entropy Coder Image Compression System, IX Spanish Symposium on Pattern Recognition and Image Processing – start-page: 724 volume-title: Proceedings of the IASTED International Conference on Modelling and Simulation year: 1997 ident: ref14 article-title: A Neural Network Based Technique for Data Compression – start-page: 43 volume-title: International Conference on Neural Networks year: 1994 ident: ref11 article-title: Image compression using a feedforward neural network – volume: 43 start-page: 138 issn: 02329298 issue: No. 11 year: 2003 ident: ref18 article-title: Image Compression Using Self-Organizing Maps publication-title: Syst Anal Model Simul doi: 10.1080/0232929032000115182 |
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| SubjectTerms | Algorithms Architecture Architecture (computers) Computer simulation Data compression Field programmable gate arrays High speed machining Image compression Image processing systems Neural networks Parallel processing Programming |
| Title | Design and VLSI Implementation of Multilayered Neural Network Architecture Using Parallel Processing and Pipelining Algorithm for Image Compression |
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