Enhanced fault detection in digital VLSI circuits using convolutional autoencoders - Savalam, Chandrasekhar; Medisetti, Sanjay; Korapati, Prasanti (Integration (Amsterdam), 2026)
As Very Large-Scale Integration (VLSI) technology advances, the demand for reliable and scalable pre-silicon fault detection (FD) techniques continues to grow. Conventional diagnostic methods often face limitations in identifying subtle stuck-at faults within complex and high-dimensional test data. This study proposes a deep learning-based fault detection framework that integrates unsupervised and supervised learning to enhance fault identification and classification in combinational circuits. A Convolutional Autoencoder (CAE) is employed to extract spatial and structural features from circuit test patterns, effectively reducing dimensionality while preserving fault-related information. The encoded features are then classified using a Random Forest model for precise fault localization. The proposed framework is validated on ISCAS’85 benchmark circuits of different sizes and complexities, achieving fault detection accuracies ranging from 93 % to 100 %. Notably, when compared to existing models such as SSAE, VAE, and CEAE, which recorded accuracies between 83 % to 98 %, the proposed CAE-Random Forest framework consistently outperformed them across all benchmarks. Furthermore, the model exhibited stable convergence, low reconstruction error, and efficient memory usage of about 380–403 MB, ensuring reliable and scalable performance. Overall, these results demonstrate that the framework offers a robust, high-accuracy, and resource-efficient solution for automatic fault detection in digital VLSI circuits. It can also be effectively extended to more complex architectures for improved diagnostic reliability. •The proposed Convolutional Autoencoder (CAE) - Random Forest framework achieved 93–100 % fault detection accuracy across ISCAS’85 benchmark circuits, outperforming SSAE, VAE, and CEAE models (83–98 %).•The CAE-based approach reached 100 % accuracy on five benchmark circuits and improved the average detection accuracy (97.4 %) compared to SSAE (93.3 %), with superior precision, recall, and F1-scores.•The unsupervised CAE effectively reduced data dimensionality while preserving fault-related spatial patterns, enabling accurate detection of subtle stuck-at faults and reducing false negatives.•The model exhibited stable convergence, low reconstruction error, and efficient memory utilization (380–403 MB), confirming its scalability and suitability for complex VLSI architectures.•Future work will focus on real-time fault detection, noise resilience, and low-power hardware deployment to enhance the applicability of the CAE framework in next-generation nano-electronics circuit testing.