Instruction-Level Parallel Processing

The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without...

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Vydáno v:Science (American Association for the Advancement of Science) Ročník 253; číslo 5025; s. 1233 - 1241
Hlavní autoři: Fisher, Joseph A., Rau, B. Ramakrshna
Médium: Journal Article
Jazyk:angličtina
Vydáno: United States American Society for the Advancement of Science 13.09.1991
American Association for the Advancement of Science
The American Association for the Advancement of Science
Témata:
Architectural education
Architecture
Central processing units
Computer programming
Computer programming & languages
Computer Science
Computer software
Computers
Control loops
CPUs (Central processing units)
Integers
Microprocessors
Musical register
Parallel computing
Parallel processing
Processor architecture
Processor architectures
Scheduling
Semiconductors
ISSN:0036-8075, 1095-9203
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Shrnutí:The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and programs, thereby enabling the tremendous proliferation of computers that we see today. To continue this performance growth, microprocessor designers have incorporated instruction-level parallelism (ILP) into new designs. ILP utilizes the parallel execution of the lowest level computer operations-adds, multiplies, loads, and so on-to increase performance transparently. The use of ILP promises to make possible, within the next few years, microprocessors whose performance is many times that of a CRAY-1S. This article provides an overview of ILP, with an emphasis on ILP architectures-superscalar, VLIW, and dataflow processors-and the compiler techniques necessary to make ILP work well.
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ISSN:0036-8075
1095-9203
DOI:10.1126/science.253.5025.1233