Instruction-Level Parallel Processing
The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without...
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| Vydáno v: | Science (American Association for the Advancement of Science) Ročník 253; číslo 5025; s. 1233 - 1241 |
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| Hlavní autoři: | , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
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United States
American Society for the Advancement of Science
13.09.1991
American Association for the Advancement of Science The American Association for the Advancement of Science |
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| ISSN: | 0036-8075, 1095-9203 |
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| Abstract | The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and programs, thereby enabling the tremendous proliferation of computers that we see today. To continue this performance growth, microprocessor designers have incorporated instruction-level parallelism (ILP) into new designs. ILP utilizes the parallel execution of the lowest level computer operations-adds, multiplies, loads, and so on-to increase performance transparently. The use of ILP promises to make possible, within the next few years, microprocessors whose performance is many times that of a CRAY-1S. This article provides an overview of ILP, with an emphasis on ILP architectures-superscalar, VLIW, and dataflow processors-and the compiler techniques necessary to make ILP work well. |
|---|---|
| AbstractList | An overview of instruction-level parallelism (ILP) is presented, focusing on ILP architectures--superscalar, very long instruction word (VLIW) processors and dataflow processors--and the compiler techniques necessary to make ILP work well. The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and programs, thereby enabling the tremendous proliferation of computers that we see today. To continue this performance growth, microprocessor designers have incorporated instruction-level parallelism (ILP) into new designs. ILP utilizes the parallel execution of the lowest level computer operations-adds, multiplies, loads, and so on-to increase performance transparently. The use of ILP promises to make possible, within the next few years, microprocessors whose performance is many times that of a CRAY-1S. This article provides an overview of ILP, with an emphasis on ILP architectures-superscalar, VLIW, and dataflow processors-and the compiler techniques necessary to make ILP work well. The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and programs, thereby enabling the tremendous proliferation of computers that we see today. To continue this performance growth, microprocessor designers have incorporated instruction-level parallelism (ILP) into new designs. ILP utilizes the parallel execution ofthe lowest level computer operations-adds, multiplies, loads, and so on-to increase performance transparently. The use of ILP promises to make possible, within the next few years, microprocessors whose performance is many times that of a CRAY-IS. This article provides an overview of ILP, with an emphasis on ILP architectures-superscalar, VLIW, and dataflow processors-and the compiler techniques necessary to make ILP work well. State of-the-art microprocessor designs incorporate instruction-level parallelism (ILP), which conducts the parallel execution of the lowest- level operation in order to maximize performance transparency. ILP is projected to be able to yield microprocessor performance levels several times greater than that of a Cray-1S. Attention is presently given to ILP superscalar, very-long-instruction-word, and dataflow processors, as well as to the compiler techniques required for ILP implementation. The simplest compiler techniques address a single basic block, and are referred to as 'local scheduling'; more complex schemes include global scheduling, loop parallelism and software pipelining, trace scheduling, and predicated execution. (O.C.) The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and programs, thereby enabling the tremendous proliferation of computers that we see today. To continue this performance growth, microprocessor designers have incorporated instruction-level parallelism (ILP) into new designs. ILP utilizes the parallel execution ofthe lowest level computer operations-adds, multiplies, loads, and so on-to increase performance transparently. The use of ILP promises to make possible, within the next few years, microprocessors whose performance is many times that of a CRAY-IS. This article provides an overview of ILP, with an emphasis on ILP architectures-superscalar, VLIW, and dataflow processors-and the compiler techniques necessary to make ILP work well.The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent fashion, that is, without requiring programmers to rethink their algorithms and programs, thereby enabling the tremendous proliferation of computers that we see today. To continue this performance growth, microprocessor designers have incorporated instruction-level parallelism (ILP) into new designs. ILP utilizes the parallel execution ofthe lowest level computer operations-adds, multiplies, loads, and so on-to increase performance transparently. The use of ILP promises to make possible, within the next few years, microprocessors whose performance is many times that of a CRAY-IS. This article provides an overview of ILP, with an emphasis on ILP architectures-superscalar, VLIW, and dataflow processors-and the compiler techniques necessary to make ILP work well. The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. To continue this performance growth, microprocessor designers have incorporated instruction-level parallelism (ILP) into new designs. ILP utilizes the parallel execution of the lowest level computer operations--adds, multiplies, loads, and so on--to increase performance transparently. This article provides an overview of ILP, with an emphasis on ILP architectures--superscalar, VLIW, and dataflow processors--and the compiler techniques necessary to make ILP work well. |
| Audience | Academic |
| Author | Rau, B. Ramakrshna Fisher, Joseph A. |
| Author_xml | – sequence: 1 givenname: Joseph A. surname: Fisher fullname: Fisher, Joseph A. – sequence: 2 givenname: B. Ramakrshna surname: Rau fullname: Rau, B. Ramakrshna |
| BackLink | https://www.ncbi.nlm.nih.gov/pubmed/17831442$$D View this record in MEDLINE/PubMed |
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| Cites_doi | 10.1145/17356.17401 10.1109/2.19820 10.1145/2465.2468 10.1147/rd.111.0008 10.1147/rd.111.0025 10.1109/12.40844 10.1109/MC.1982.1653940 |
| ContentType | Journal Article |
| Copyright | Copyright 1991 American Association for the Advancement of Science COPYRIGHT 1991 American Association for the Advancement of Science COPYRIGHT 1991 American Association for the Advancement of Science Copyright American Association for the Advancement of Science Sep 13, 1991 |
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| DOI | 10.1126/science.253.5025.1233 |
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| Snippet | The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. This is the cumulative result of... An overview of instruction-level parallelism (ILP) is presented, focusing on ILP architectures--superscalar, very long instruction word (VLIW) processors and... The performance of microprocessors has increased steadily over the past 20 years at a rate of about 50% per year. To continue this performance growth,... State of-the-art microprocessor designs incorporate instruction-level parallelism (ILP), which conducts the parallel execution of the lowest- level operation... |
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| SubjectTerms | Architectural education Architecture Central processing units Computer programming Computer programming & languages Computer Science Computer software Computers Control loops CPUs (Central processing units) Integers Microprocessors Musical register Parallel computing Parallel processing Processor architecture Processor architectures Scheduling Semiconductors |
| Title | Instruction-Level Parallel Processing |
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| Volume | 253 |
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