A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

In this paper, a new architecture is proposed for multiplier and Accumulator to increase the arithmetic operation. Multiplication and accumulation will help in improving the performance of multiplier. The Radix-2 modified booth algorithm is used for the reduction of partial products. The parallel mu...

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Vydáno v:I-Manager's Journal on Circuits & Systems Ročník 5; číslo 3; s. 38
Hlavní autoři: ISHITA, VERMA, PRIYANKA, GHOSH, UPENDRA, SONI, DHARMENDRA, SINGH
Médium: Journal Article
Jazyk:angličtina
Vydáno: Nagercoil iManager Publications 01.06.2017
Témata:
Accumulators
Algorithms
Architecture
Arithmetic
High speed
ISSN:2321-7502, 2322-035X
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Shrnutí:In this paper, a new architecture is proposed for multiplier and Accumulator to increase the arithmetic operation. Multiplication and accumulation will help in improving the performance of multiplier. The Radix-2 modified booth algorithm is used for the reduction of partial products. The parallel multiplier can be such as radix 2 modified booth algorithm is used to improve the computations; this can be achieved using fewer adder and steps. By using Radix-2 modified booth multiplier algorithm the high speed of operation can be achieved.
Bibliografie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:2321-7502
2322-035X
DOI:10.26634/jcir.5.3.13866