A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM
In this paper, a new architecture is proposed for multiplier and Accumulator to increase the arithmetic operation. Multiplication and accumulation will help in improving the performance of multiplier. The Radix-2 modified booth algorithm is used for the reduction of partial products. The parallel mu...
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| Published in: | I-Manager's Journal on Circuits & Systems Vol. 5; no. 3; p. 38 |
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| Main Authors: | , , , |
| Format: | Journal Article |
| Language: | English |
| Published: |
Nagercoil
iManager Publications
01.06.2017
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| Subjects: | |
| ISSN: | 2321-7502, 2322-035X |
| Online Access: | Get full text |
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