A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

In this paper, a new architecture is proposed for multiplier and Accumulator to increase the arithmetic operation. Multiplication and accumulation will help in improving the performance of multiplier. The Radix-2 modified booth algorithm is used for the reduction of partial products. The parallel mu...

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Veröffentlicht in:	I-Manager's Journal on Circuits & Systems Jg. 5; H. 3; S. 38
Hauptverfasser:	ISHITA, VERMA, PRIYANKA, GHOSH, UPENDRA, SONI, DHARMENDRA, SINGH
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Nagercoil iManager Publications 01.06.2017
Schlagworte:	Accumulators Algorithms Architecture Arithmetic High speed
ISSN:	2321-7502, 2322-035X
Online-Zugang:	Volltext
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