A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

In this paper, a new architecture is proposed for multiplier and Accumulator to increase the arithmetic operation. Multiplication and accumulation will help in improving the performance of multiplier. The Radix-2 modified booth algorithm is used for the reduction of partial products. The parallel mu...

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Vydáno v:I-Manager's Journal on Circuits & Systems Ročník 5; číslo 3; s. 38
Hlavní autoři: ISHITA, VERMA, PRIYANKA, GHOSH, UPENDRA, SONI, DHARMENDRA, SINGH
Médium: Journal Article
Jazyk:angličtina
Vydáno: Nagercoil iManager Publications 01.06.2017
Témata:
Accumulators
Algorithms
Architecture
Arithmetic
High speed
ISSN:2321-7502, 2322-035X
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Abstract In this paper, a new architecture is proposed for multiplier and Accumulator to increase the arithmetic operation. Multiplication and accumulation will help in improving the performance of multiplier. The Radix-2 modified booth algorithm is used for the reduction of partial products. The parallel multiplier can be such as radix 2 modified booth algorithm is used to improve the computations; this can be achieved using fewer adder and steps. By using Radix-2 modified booth multiplier algorithm the high speed of operation can be achieved.
AbstractList In this paper, a new architecture is proposed for multiplier and Accumulator to increase the arithmetic operation. Multiplication and accumulation will help in improving the performance of multiplier. The Radix-2 modified booth algorithm is used for the reduction of partial products. The parallel multiplier can be such as radix 2 modified booth algorithm is used to improve the computations; this can be achieved using fewer adder and steps. By using Radix-2 modified booth multiplier algorithm the high speed of operation can be achieved.
Author ISHITA, VERMA
UPENDRA, SONI
DHARMENDRA, SINGH
PRIYANKA, GHOSH
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Cites_doi 10.1201/9781420049671.ch18
10.1109/ICIAS.2012.6306130
10.1109/ARVLSI.1999.756051
10.1166/jolpe.2005.046
10.1109/12.192219
10.1109/ICCCA.2012.6179170
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CorporateAuthor Assistant Professor, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Bhilai, India
UG Scholar, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Bhilai, India
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SubjectTerms Accumulators
Algorithms
Architecture
Arithmetic
High speed
Title A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM
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