ISHITA, V., PRIYANKA, G., UPENDRA, S., & DHARMENDRA, S. (2017). A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM. I-Manager's Journal on Circuits & Systems, 5(3), 38. https://doi.org/10.26634/jcir.5.3.13866
Citace podle Chicago (17th ed.)ISHITA, VERMA, GHOSH PRIYANKA, SONI UPENDRA, a SINGH DHARMENDRA. "A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM." I-Manager's Journal on Circuits & Systems 5, no. 3 (2017): 38. https://doi.org/10.26634/jcir.5.3.13866.
Citace podle MLA (9th ed.)ISHITA, VERMA, et al. "A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM." I-Manager's Journal on Circuits & Systems, vol. 5, no. 3, 2017, p. 38, https://doi.org/10.26634/jcir.5.3.13866.