A graph placement methodology for fast chip design

Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research 1 , chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep rei...

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Vydáno v:	Nature (London) Ročník 594; číslo 7862; s. 207 - 212
Hlavní autoři:	Mirhoseini, Azalia, Goldie, Anna, Yazgan, Mustafa, Jiang, Joe Wenjie, Songhori, Ebrahim, Wang, Shen, Lee, Young-Joon, Johnson, Eric, Pathak, Omkar, Nova, Azade, Pak, Jiwoo, Tong, Andy, Srinivasa, Kavya, Hang, William, Tuncer, Emre, Le, Quoc V., Laudon, James, Ho, Richard, Carpenter, Roger, Dean, Jeff
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	London Nature Publishing Group UK 10.06.2021 Nature Publishing Group
Témata:	639/166/987 639/705/1042 Accelerators Agents (artificial intelligence) Artificial intelligence Artificial neural networks Automation Computer architecture Design Design and construction Design for manufacturability Floorplans Graph theory Humanities and Social Sciences Integrated circuits Layouts Learning Machine learning multidisciplinary Neural networks Power consumption Reinforcement Science Science (multidisciplinary) Semiconductor chips United States
ISSN:	0028-0836, 1476-4687, 1476-4687
On-line přístup:	Získat plný text
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