Hardware implementation of memristor-based artificial neural networks
Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not...
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| Published in: | Nature communications Vol. 15; no. 1; pp. 1974 - 40 |
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| Main Authors: | , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , |
| Format: | Journal Article |
| Language: | English |
| Published: |
London
Nature Publishing Group UK
04.03.2024
Nature Publishing Group Nature Portfolio |
| Subjects: | |
| ISSN: | 2041-1723, 2041-1723 |
| Online Access: | Get full text |
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| Abstract | Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.
Memristors hold promise for massively-parallel computing at low power. Aguirre et al. provide a comprehensive protocol of the materials and methods for designing memristive artificial neural networks with the detailed working principles of each building block and the tools for performance evaluation. |
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| AbstractList | Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach. Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach. Memristors hold promise for massively-parallel computing at low power. Aguirre et al. provide a comprehensive protocol of the materials and methods for designing memristive artificial neural networks with the detailed working principles of each building block and the tools for performance evaluation. Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach. Memristors hold promise for massively-parallel computing at low power. Aguirre et al. provide a comprehensive protocol of the materials and methods for designing memristive artificial neural networks with the detailed working principles of each building block and the tools for performance evaluation. Abstract Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach. Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach. |
| ArticleNumber | 1974 |
| Author | Lu, Wei Miranda, Enrique Le Gallo, Manuel Hsu, Hung-Hsi Aguirre, Fernando Yan, Xiaobing Krestinskaya, Olga Eltawil, Ahmed Sebastian, Abu Salama, Khaled N. Mehonic, Adnan Villena, Marco A. Yang, Yuchao Wu, Yuting Smagulova, Kamilya Raghavan, Nagarajan Setti, Gianluca Alharbi, Osamah Kenyon, Anthony Lanza, Mario Wang, Tong Roldán, Juan B. Suñé, Jordi Li, Sifan Ielmini, Daniele Song, Wenhao Ang, Kah-Wee Chang, Meng-Fan Jain, Samarth Pazos, Sebastian Yang, J. Joshua |
| Author_xml | – sequence: 1 givenname: Fernando surname: Aguirre fullname: Aguirre, Fernando organization: Physical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST), Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB) – sequence: 2 givenname: Abu orcidid: 0000-0001-5603-5243 surname: Sebastian fullname: Sebastian, Abu organization: IBM Research – Zurich – sequence: 3 givenname: Manuel orcidid: 0000-0003-1600-6151 surname: Le Gallo fullname: Le Gallo, Manuel organization: IBM Research – Zurich – sequence: 4 givenname: Wenhao surname: Song fullname: Song, Wenhao organization: Department of Electrical and Computer Engineering, University of Southern California (USC) – sequence: 5 givenname: Tong surname: Wang fullname: Wang, Tong organization: Department of Electrical and Computer Engineering, University of Southern California (USC) – sequence: 6 givenname: J. Joshua orcidid: 0000-0001-8242-7531 surname: Yang fullname: Yang, J. Joshua organization: Department of Electrical and Computer Engineering, University of Southern California (USC) – sequence: 7 givenname: Wei surname: Lu fullname: Lu, Wei organization: Department of Electrical Engineering and Computer Science, University of Michigan – sequence: 8 givenname: Meng-Fan orcidid: 0000-0001-6905-6350 surname: Chang fullname: Chang, Meng-Fan organization: Department of Electrical Engineering, National Tsing Hua University – sequence: 9 givenname: Daniele orcidid: 0000-0002-1853-1614 surname: Ielmini fullname: Ielmini, Daniele organization: Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano and IUNET – sequence: 10 givenname: Yuchao orcidid: 0000-0003-4674-4059 surname: Yang fullname: Yang, Yuchao organization: School of Electronic and Computer Engineering, Peking University – sequence: 11 givenname: Adnan orcidid: 0000-0002-2476-5038 surname: Mehonic fullname: Mehonic, Adnan organization: Department of Electronic and Electrical Engineering, University College London (UCL), Torrington Place – sequence: 12 givenname: Anthony orcidid: 0000-0003-2249-2184 surname: Kenyon fullname: Kenyon, Anthony organization: Department of Electronic and Electrical Engineering, University College London (UCL), Torrington Place – sequence: 13 givenname: Marco A. orcidid: 0000-0001-5547-3380 surname: Villena fullname: Villena, Marco A. organization: Physical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST) – sequence: 14 givenname: Juan B. orcidid: 0000-0003-1662-6457 surname: Roldán fullname: Roldán, Juan B. organization: Departamento de Electrónica y Tecnología de Computadores, Facultad de Ciencias, Universidad de Granada, Avenida Fuentenueva s/n – sequence: 15 givenname: Yuting surname: Wu fullname: Wu, Yuting organization: Department of Electrical Engineering and Computer Science, University of Michigan – sequence: 16 givenname: Hung-Hsi surname: Hsu fullname: Hsu, Hung-Hsi organization: Department of Electrical Engineering, National Tsing Hua University – sequence: 17 givenname: Nagarajan surname: Raghavan fullname: Raghavan, Nagarajan organization: Engineering Product Development (EPD) Pillar, Singapore University of Technology & Design – sequence: 18 givenname: Jordi orcidid: 0000-0003-0108-4907 surname: Suñé fullname: Suñé, Jordi organization: Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB) – sequence: 19 givenname: Enrique surname: Miranda fullname: Miranda, Enrique organization: Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB) – sequence: 20 givenname: Ahmed orcidid: 0000-0003-1849-083X surname: Eltawil fullname: Eltawil, Ahmed organization: Computer, Electrical and Mathematical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST) – sequence: 21 givenname: Gianluca surname: Setti fullname: Setti, Gianluca organization: Computer, Electrical and Mathematical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST) – sequence: 22 givenname: Kamilya surname: Smagulova fullname: Smagulova, Kamilya organization: Computer, Electrical and Mathematical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST) – sequence: 23 givenname: Khaled N. orcidid: 0000-0001-7742-1282 surname: Salama fullname: Salama, Khaled N. organization: Computer, Electrical and Mathematical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST) – sequence: 24 givenname: Olga orcidid: 0000-0001-8038-4558 surname: Krestinskaya fullname: Krestinskaya, Olga organization: Computer, Electrical and Mathematical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST) – sequence: 25 givenname: Xiaobing orcidid: 0000-0002-6335-336X surname: Yan fullname: Yan, Xiaobing organization: Key Laboratory of Brain-Like Neuromorphic Devices and Systems of Hebei Province, Hebei University – sequence: 26 givenname: Kah-Wee surname: Ang fullname: Ang, Kah-Wee organization: Department of Electrical and Computer Engineering, College of Design and Engineering, National University of Singapore (NUS) – sequence: 27 givenname: Samarth surname: Jain fullname: Jain, Samarth organization: Department of Electrical and Computer Engineering, College of Design and Engineering, National University of Singapore (NUS) – sequence: 28 givenname: Sifan surname: Li fullname: Li, Sifan organization: Department of Electrical and Computer Engineering, College of Design and Engineering, National University of Singapore (NUS) – sequence: 29 givenname: Osamah orcidid: 0000-0003-1660-0310 surname: Alharbi fullname: Alharbi, Osamah organization: Physical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST) – sequence: 30 givenname: Sebastian orcidid: 0000-0002-7354-4530 surname: Pazos fullname: Pazos, Sebastian organization: Physical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST) – sequence: 31 givenname: Mario orcidid: 0000-0003-4756-8632 surname: Lanza fullname: Lanza, Mario email: mario.lanza@kaust.edu.sa organization: Physical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST) |
| BackLink | https://www.ncbi.nlm.nih.gov/pubmed/38438350$$D View this record in MEDLINE/PubMed |
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| Snippet | Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing... Abstract Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple... |
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| Title | Hardware implementation of memristor-based artificial neural networks |
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