Parametric Dense Stereovision Implementation on a System-on Chip (SoC)

This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC) provi...

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Vydáno v:Sensors (Basel, Switzerland) Ročník 12; číslo 2; s. 1863 - 1884
Hlavní autoři: Gardel, Alfredo, Montejo, Pablo, García, Jorge, Bravo, Ignacio, Lázaro, José L.
Médium: Journal Article
Jazyk:angličtina
Vydáno: Switzerland MDPI AG 01.02.2012
Molecular Diversity Preservation International (MDPI)
Témata:
Algorithms
Cameras
correlation
correspondence
Entropy
Equipment Design
Equipment Failure Analysis
Geometry
Imaging, Three-Dimensional - instrumentation
Information Storage and Retrieval - methods
Photogrammetry - instrumentation
real-time processing
reconfigurable hardware
Sensors
Signal Processing, Computer-Assisted - instrumentation
stereovision
entropy
correlation
real-time processing
stereovision
correspondence
reconfigurable hardware
ISSN:1424-8220, 1424-8220
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Shrnutí:This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC) provides great performance and efficiency, with a scalable architecture available for many different situations, addressing real time processing of stereo image flow. Using double buffering techniques properly combined with pipelined processing, the use of reconfigurable hardware achieves a parametrisable SoC which gives the designer the opportunity to decide its right dimension and features. The proposed architecture does not need any external memory because the processing is done as image flow arrives. Our SoC provides 3D data directly without the storage of whole stereo images. Our goal is to obtain high processing speed while maintaining the accuracy of 3D data using minimum resources. Configurable parameters may be controlled by later/parallel stages of the vision algorithm executed on an embedded processor. Considering hardware FPGA clock of 100 MHz, image flows up to 50 frames per second (fps) of dense stereo maps of more than 30,000 depth points could be obtained considering 2 Mpix images, with a minimum initial latency. The implementation of computer vision algorithms on reconfigurable hardware, explicitly low level processing, opens up the prospect of its use in autonomous systems, and they can act as a coprocessor to reconstruct 3D images with high density information in real time.
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ISSN:1424-8220
1424-8220
DOI:10.3390/s120201863