System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies

Modern system-on-chip (SOC) designs consist of numerous heterogeneous components (embedded CPUs, dedicated hardware, FPGAs, embedded memories and so on) integrated onto a single chip. The on-chip communication is becoming the bottleneck for these SOC designs, and efficient contention resolution sche...

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Vydáno v:IET computers & digital techniques Ročník 1; číslo 1; s. 1 - 8
Hlavní autoři: Wang, N., Bayoumi, M.A.
Médium: Journal Article
Jazyk:angličtina
Vydáno: Stevenage Institution of Engineering and Technology 01.01.2007
John Wiley & Sons, Inc
Témata:
Applied sciences
Architecture
Architecture (computers)
Buses
Circuit properties
Communication systems
Control systems
Data buses
Design engineering
Design. Technologies. Operation analysis. Testing
Digital circuits
Dynamical systems
Dynamics
Electric, optical and optoelectronic circuits
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
System on chip
Performance evaluation
Processor
Prototype
Scalability
Control synthesis
Field programmable gate array
System on a chip
Parallel architectures
Bus(channel)
Embedded systems
Interconnection
Integrated circuit
Parallel processing
Damaging
ISSN:1751-8601, 1751-861X
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Popis
Shrnutí:Modern system-on-chip (SOC) designs consist of numerous heterogeneous components (embedded CPUs, dedicated hardware, FPGAs, embedded memories and so on) integrated onto a single chip. The on-chip communication is becoming the bottleneck for these SOC designs, and efficient contention resolution schemes for managing simultaneous access requests to the communication resources are required to prevent system performance degradation. A new SOC on-chip communication architecture, Dynamic Parallel Fraction Control Bus, which offers an attractive solution for the problem and addresses shortcomings of existing communication architectures is presented. To demonstrate the benefits of the proposed architecture, several existing communication architectures were compared with the proposed architecture on the basis of two application prototypes. Through experimentation it has been shown that the proposed architecture not only exhibits both hardware simplicity and system performance improvements, but also produces better bus bandwidth control and scalability properties compared with the existing communication architectures.
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ISSN:1751-8601
1751-861X
DOI:10.1049/iet-cdt:20060080