System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies
Modern system-on-chip (SOC) designs consist of numerous heterogeneous components (embedded CPUs, dedicated hardware, FPGAs, embedded memories and so on) integrated onto a single chip. The on-chip communication is becoming the bottleneck for these SOC designs, and efficient contention resolution sche...
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| Published in: | IET computers & digital techniques Vol. 1; no. 1; pp. 1 - 8 |
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| Main Authors: | , |
| Format: | Journal Article |
| Language: | English |
| Published: |
Stevenage
Institution of Engineering and Technology
01.01.2007
John Wiley & Sons, Inc |
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| ISSN: | 1751-8601, 1751-861X |
| Online Access: | Get full text |
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| Abstract | Modern system-on-chip (SOC) designs consist of numerous heterogeneous components (embedded CPUs, dedicated hardware, FPGAs, embedded memories and so on) integrated onto a single chip. The on-chip communication is becoming the bottleneck for these SOC designs, and efficient contention resolution schemes for managing simultaneous access requests to the communication resources are required to prevent system performance degradation. A new SOC on-chip communication architecture, Dynamic Parallel Fraction Control Bus, which offers an attractive solution for the problem and addresses shortcomings of existing communication architectures is presented. To demonstrate the benefits of the proposed architecture, several existing communication architectures were compared with the proposed architecture on the basis of two application prototypes. Through experimentation it has been shown that the proposed architecture not only exhibits both hardware simplicity and system performance improvements, but also produces better bus bandwidth control and scalability properties compared with the existing communication architectures. |
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| AbstractList | Modern system-on-chip (SOC) designs consist of numerous heterogeneous components (embedded CPUs, dedicated hardware, FPGAs, embedded memories and so on) integrated onto a single chip. The on-chip communication is becoming the bottleneck for these SOC designs, and efficient contention resolution schemes for managing simultaneous access requests to the communication resources are required to prevent system performance degradation. A new SOC on-chip communication architecture, Dynamic Parallel Fraction Control Bus, which offers an attractive solution for the problem and addresses shortcomings of existing communication architectures is presented. To demonstrate the benefits of the proposed architecture, several existing communication architectures were compared with the proposed architecture on the basis of two application prototypes. Through experimentation it has been shown that the proposed architecture not only exhibits both hardware simplicity and system performance improvements, but also produces better bus bandwidth control and scalability properties compared with the existing communication architectures. |
| Author | Wang, N. Bayoumi, M.A. |
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| Keywords | Performance evaluation Processor Prototype Scalability Control synthesis Field programmable gate array System on a chip Parallel architectures Bus(channel) Embedded systems Interconnection Integrated circuit Parallel processing Damaging |
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| References | Turner (10.1049/iet-cdt:20060080_r19) 1998; E-81B Kavaldjiev (10.1049/iet-cdt:20060080_r6) 2004 10.1049/iet-cdt:20060080_r10 10.1049/iet-cdt:20060080_r21 10.1049/iet-cdt:20060080_r11 Lahiri (10.1049/iet-cdt:20060080_r16) 2001 10.1049/iet-cdt:20060080_r3 Zhao (10.1049/iet-cdt:20060080_r7) 2006 10.1049/iet-cdt:20060080_r1 10.1049/iet-cdt:20060080_r12 10.1049/iet-cdt:20060080_r13 10.1049/iet-cdt:20060080_r14 Poletti (10.1049/iet-cdt:20060080_r2) 2003 10.1049/iet-cdt:20060080_r15 Anjo (10.1049/iet-cdt:20060080_r5) 2004 Lee (10.1049/iet-cdt:20060080_r4) 2003 10.1049/iet-cdt:20060080_r9 10.1049/iet-cdt:20060080_r8 Wang (10.1049/iet-cdt:20060080_r20) 2005 Webber (10.1049/iet-cdt:20060080_r18) 2005 Lee (10.1049/iet-cdt:20060080_r17) 2004 |
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| SubjectTerms | Applied sciences Architecture Architecture (computers) Buses Circuit properties Communication systems Control systems Data buses Design engineering Design. Technologies. Operation analysis. Testing Digital circuits Dynamical systems Dynamics Electric, optical and optoelectronic circuits Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices System on chip |
| Title | System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies |
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