Routing Brain Traffic Through the Von Neumann Bottleneck: Parallel Sorting and Refactoring

Generic simulation code for spiking neuronal networks spends the major part of the time in the phase where spikes have arrived at a compute node and need to be delivered to their target neurons. These spikes were emitted over the last interval between communication steps by source neurons distribute...

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Vydané v:	Frontiers in neuroinformatics Ročník 15; s. 785068
Hlavní autori:	Pronold, Jari, Jordan, Jakob, Wylie, Brian J. N., Kitayama, Itaru, Diesmann, Markus, Kunkel, Susanne
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Switzerland Frontiers Research Foundation 01.03.2022 Frontiers Media S.A
Predmet:	Algorithms Communication Computer programs distributed computing Firing pattern irregular access pattern large-scale simulation Latency Memory Neural networks Neurons Neuroscience parallel computing Simulation Software Sparsity spiking neural networks Synchronization irregular access pattern large-scale simulation spiking neural networks memory-access bottleneck sparsity parallel computing distributed computing
ISSN:	1662-5196, 1662-5196
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Shrnutí:	Generic simulation code for spiking neuronal networks spends the major part of the time in the phase where spikes have arrived at a compute node and need to be delivered to their target neurons. These spikes were emitted over the last interval between communication steps by source neurons distributed across many compute nodes and are inherently irregular and unsorted with respect to their targets. For finding those targets, the spikes need to be dispatched to a three-dimensional data structure with decisions on target thread and synapse type to be made on the way. With growing network size, a compute node receives spikes from an increasing number of different source neurons until in the limit each synapse on the compute node has a unique source. Here, we show analytically how this sparsity emerges over the practically relevant range of network sizes from a hundred thousand to a billion neurons. By profiling a production code we investigate opportunities for algorithmic changes to avoid indirections and branching. Every thread hosts an equal share of the neurons on a compute node. In the original algorithm, all threads search through all spikes to pick out the relevant ones. With increasing network size, the fraction of hits remains invariant but the absolute number of rejections grows. Our new alternative algorithm equally divides the spikes among the threads and immediately sorts them in parallel according to target thread and synapse type. After this, every thread completes delivery solely of the section of spikes for its own neurons. Independent of the number of threads, all spikes are looked at only two times. The new algorithm halves the number of instructions in spike delivery which leads to a reduction of simulation time of up to 40 %. Thus, spike delivery is a fully parallelizable process with a single synchronization point and thereby well suited for many-core systems. Our analysis indicates that further progress requires a reduction of the latency that the instructions experience in accessing memory. The study provides the foundation for the exploration of methods of latency hiding like software pipelining and software-induced prefetching.
Bibliografia:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 content type line 23 Reviewed by: Stavros I. Dimitriadis, Greek Association of Alzheimer's Disease and Related Disorders, Greece; Jiang Wang, Tianjin University, China; Antonio Marcos Batista, Universidade Estadual de Ponta Grossa, Brazil Edited by: Ludovico Minati, Tokyo Institute of Technology, Japan
ISSN:	1662-5196 1662-5196
DOI:	10.3389/fninf.2021.785068