FPGA Implementation of A∗ Algorithm for Real-Time Path Planning

The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in f...

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Bibliographic Details
Published in:International Journal of Reconfigurable Computing Vol. 2020; no. 2020; pp. 1 - 11
Main Authors: Zhou, Yuzhi, Wang, Tianqi, Jin, Xi
Format: Journal Article
Language:English
Published: Cairo, Egypt Hindawi Publishing Corporation 2020
Hindawi
John Wiley & Sons, Inc
Wiley
Subjects:
Algorithms
Digital integrated circuits
Field programmable gate arrays
Hardware
Heuristic
Mathematical analysis
Path planning
Performance enhancement
Real time
Robotics
Semiconductor industry
Software
System on chip
Technology application
United States
ISSN:1687-7195, 1687-7209
Online Access:Get full text
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Summary:The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator. Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications.
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ISSN:1687-7195
1687-7209
DOI:10.1155/2020/8896386