Migration in Hardware Transactional Memory on Asymmetric Multiprocessor

In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid pu...

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Bibliographic Details
Published in:IEEE access Vol. 9; pp. 69346 - 69364
Main Authors: Sustran, Zivojin, Protic, Jelica
Format: Journal Article
Language:English
Published: Piscataway IEEE 2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
asymmetric multiprocessor
Asymmetry
Hardware
hardware transactional memory
Instruction sets
multicore architectures
Multicore processing
Multiprocessing
Parallel processing
Power demand
Scheduling
Shared memory algorithms
Synchronization
thread migration
ISSN:2169-3536, 2169-3536
Online Access:Get full text
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Summary:In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid putting additional burden on a programmer. Therefore, the proposed solution should be fully implemented in hardware. In the asymmetric multiprocessor that is analyzed, all cores have the same instruction set, but they are asymmetric in terms of microarchitectural properties, so that N −1 "small" cores are identical, while the <inline-formula> <tex-math notation="LaTeX">\text{N}^{\mathrm {th}} </tex-math></inline-formula> "big" core is different, as it provides better performance and higher capacities of its units. The idea is to perform transaction migration from the "small" core to the "big" one, based on the history of transaction execution. The experiments were performed using a significantly upgraded Gem5 simulator and eight parallel applications from the STAMP benchmark suite. The experimental results show the speedup and the rate of successfully executed transactions for five different multiprocessor configurations, including symmetric and asymmetric multiprocessors with or without transaction migration. The improvement our algorithm achieves for suitable applications is up to 14% (10% on average) in turnaround time compared to the solutions which do not make use of asymmetry for scheduling transactions.
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ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2021.3077539