Migration in Hardware Transactional Memory on Asymmetric Multiprocessor

In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid pu...

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Bibliographic Details

Published in:	IEEE access Vol. 9; pp. 69346 - 69364
Main Authors:	Sustran, Zivojin, Protic, Jelica
Format:	Journal Article
Language:	English
Published:	Piscataway IEEE 2021 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithms asymmetric multiprocessor Asymmetry Hardware hardware transactional memory Instruction sets multicore architectures Multicore processing Multiprocessing Parallel processing Power demand Scheduling Shared memory algorithms Synchronization thread migration
ISSN:	2169-3536, 2169-3536
Online Access:	Get full text
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