Migration in Hardware Transactional Memory on Asymmetric Multiprocessor

In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid pu...

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Vydáno v:	IEEE access Ročník 9; s. 69346 - 69364
Hlavní autoři:	Sustran, Zivojin, Protic, Jelica
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Piscataway IEEE 2021 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Algorithms asymmetric multiprocessor Asymmetry Hardware hardware transactional memory Instruction sets multicore architectures Multicore processing Multiprocessing Parallel processing Power demand Scheduling Shared memory algorithms Synchronization thread migration
ISSN:	2169-3536, 2169-3536
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