Joint detection–decoding of majority-logic decodable non-binary low-density parity-check coded modulation systems: an iterative noise reduction algorithm

In this study, the authors present a low-complexity iterative joint detection–decoding algorithm for majority-logic decodable non-binary low-density parity-check (LDPC) coded modulation systems. In the proposed algorithm, a hard-in–hard-out decoder is combined with a hard-decision signal detector in...

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Vydáno v:	IET communications Ročník 8; číslo 10; s. 1810 - 1819
Hlavní autoři:	Zhao, Shancheng, Wang, Xuepeng, Wang, Teng, Bai, Baoming, Ma, Xiao
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Stevenage The Institution of Engineering and Technology 01.07.2014 John Wiley & Sons, Inc
Témata:	adjacent check nodes Algorithms combinational circuits combinational logic circuits Decisions Error correcting codes flnite fleld operations hard extrinsic message computation hard‐decision signal detector hard‐in‐hard‐out decoder integer operations iterative decoding Iterative methods iterative noise reduction algorithm iteratively updated received signals LDPC low‐complexity iterative joint detection‐decoding algorithm majority‐logic decodable low‐density parity‐check coded modulation system Mathematical models Messages Modulation modulation coding Noise reduction nonbinary low‐density parity‐check coded modulation system parity check codes signal denoising signal detection variable nodes nonbinary low-density parity-check coded modulation system signal detection modulation coding combinational circuits parity check codes LDPC adjacent check nodes hard-decision signal detector hard-in-hard-out decoder majority-logic decodable low-density parity-check coded modulation system variable nodes signal denoising iterative noise reduction algorithm integer operations iterative decoding hard extrinsic message computation flnite fleld operations combinational logic circuits low-complexity iterative joint detection-decoding algorithm iteratively updated received signals
ISSN:	1751-8628, 1751-8636
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Shrnutí:	In this study, the authors present a low-complexity iterative joint detection–decoding algorithm for majority-logic decodable non-binary low-density parity-check (LDPC) coded modulation systems. In the proposed algorithm, a hard-in–hard-out decoder is combined with a hard-decision signal detector in an iterative manner. Each iteration consists of five phases. Firstly, the detector makes hard decisions based on the iteratively updated ‘received’ signals; secondly, these hard decisions are distributed via variable nodes to check nodes; thirdly, check nodes compute hard extrinsic messages; fourthly, each variable node counts hard extrinsic messages from its adjacent check nodes and feeds back to the detection node the symbol with the most votes as well as the difference between the most votes and the second most votes; finally, these feedbacks are used to shift each ‘received’ signal point along an estimated direction to possibly reduce noise. The proposed algorithm requires only integer operations and finite field operations and consequently can be implemented with simple combinational logic circuits in practical systems. Simulation results show that the proposed algorithm performs well and hence serves as an attractive candidate for trading off performance against complexity for majority-logic decodable non-binary LDPC codes.
Bibliografie:	SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 ObjectType-Article-1 ObjectType-Feature-2 content type line 23
ISSN:	1751-8628 1751-8636
DOI:	10.1049/iet-com.2013.0684