IP core implementation of a self-organizing neural network
This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-/spl mu/m single silicon chip providing an array of 256 neurons, where each neuron stores a...
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| Veröffentlicht in: | IEEE transactions on neural networks Jg. 14; H. 5; S. 1085 - 1096 |
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| Sprache: | Englisch |
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01.09.2003
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| ISSN: | 1045-9227 |
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| Abstract | This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-/spl mu/m single silicon chip providing an array of 256 neurons, where each neuron stores a 16 element reference vector. Migrating the design to a soft IP core presents challenges in achieving the required performance as regards area, power, and clock speed. This same migration, however, offers opportunities for parameterizing the design in a manner which permits a single soft core to meet the requirements of many end users. Thus, the number of neurons within the single instruction multiple data (SIMD) array, the number of elements per reference vector, and the number of bits of each such element are defined by synthesis time parameters. The construction of the SIMD array of neurons is presented including performance results as regards power, area, and classifications per second . For typical parameters (256 neurons with 16 elements per reference vector) the design provides over 2 000 000 classifications per second using a mainstream 0.18-/spl mu/m digital process. A RISC processor, the array controller (AC), provides both the instruction stream and data to the SIMD array of neurons and an interface to a host processor. The design of this processor is discussed with emphasis on the control aspects which permit supply of a continuous instruction stream to the SIMD array and a flexible interface with the host processor. |
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| AbstractList | This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-/spl mu/m single silicon chip providing an array of 256 neurons, where each neuron stores a 16 element reference vector. Migrating the design to a soft IP core presents challenges in achieving the required performance as regards area, power, and clock speed. This same migration, however, offers opportunities for parameterizing the design in a manner which permits a single soft core to meet the requirements of many end users. Thus, the number of neurons within the single instruction multiple data (SIMD) array, the number of elements per reference vector, and the number of bits of each such element are defined by synthesis time parameters. The construction of the SIMD array of neurons is presented including performance results as regards power, area, and classifications per second . For typical parameters (256 neurons with 16 elements per reference vector) the design provides over 2 000 000 classifications per second using a mainstream 0.18-/spl mu/m digital process. A RISC processor, the array controller (AC), provides both the instruction stream and data to the SIMD array of neurons and an interface to a host processor. The design of this processor is discussed with emphasis on the control aspects which permit supply of a continuous instruction stream to the SIMD array and a flexible interface with the host processor. This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-/spl mu/m single silicon chip providing an array of 256 neurons, where each neuron stores a 16 element reference vector. Migrating the design to a soft IP core presents challenges in achieving the required performance as regards area, power, and clock speed. This same migration, however, offers opportunities for parameterizing the design in a manner which permits a single soft core to meet the requirements of many end users. Thus, the number of neurons within the single instruction multiple data (SIMD) array, the number of elements per reference vector, and the number of bits of each such element are defined by synthesis time parameters. The construction of the SIMD array of neurons is presented including performance results as regards power, area, and classifications per second . For typical parameters (256 neurons with 16 elements per reference vector) the design provides over 2 000 000 classifications per second using a mainstream 0.18-/spl mu/m digital process. A RISC processor, the array controller (AC), provides both the instruction stream and data to the SIMD array of neurons and an interface to a host processor. The design of this processor is discussed with emphasis on the control aspects which permit supply of a continuous instruction stream to the SIMD array and a flexible interface with the host processor.This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-/spl mu/m single silicon chip providing an array of 256 neurons, where each neuron stores a 16 element reference vector. Migrating the design to a soft IP core presents challenges in achieving the required performance as regards area, power, and clock speed. This same migration, however, offers opportunities for parameterizing the design in a manner which permits a single soft core to meet the requirements of many end users. Thus, the number of neurons within the single instruction multiple data (SIMD) array, the number of elements per reference vector, and the number of bits of each such element are defined by synthesis time parameters. The construction of the SIMD array of neurons is presented including performance results as regards power, area, and classifications per second . For typical parameters (256 neurons with 16 elements per reference vector) the design provides over 2 000 000 classifications per second using a mainstream 0.18-/spl mu/m digital process. A RISC processor, the array controller (AC), provides both the instruction stream and data to the SIMD array of neurons and an interface to a host processor. The design of this processor is discussed with emphasis on the control aspects which permit supply of a continuous instruction stream to the SIMD array and a flexible interface with the host processor. This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65-mum single silicon chip providing an array of 256 neurons, where each neuron stores a 16 element reference vector. Migrating the design to a soft IP core presents challenges in achieving the required performance as regards area, power, and clock speed. This same migration, however, offers opportunities for parameterizing the design in a manner which permits a single soft core to meet the requirements of many end users. Thus, the number of neurons within the single instruction multiple data (SIMD) array, the number of elements per reference vector, and the number of bits of each such element are defined by synthesis time parameters. The construction of the SIMD array of neurons is presented including performance results as regards power, area, and classifications per second . For typical parameters (256 neurons with 16 elements per reference vector) the design provides over 2 000 000 classifications per second using a mainstream 0.18-mum digital process. A RISC processor, the array controller (AC), provides both the instruction stream and data to the SIMD array of neurons and an interface to a host processor. The design of this processor is discussed with emphasis on the control aspects which permit supply of a continuous instruction stream to the SIMD array and a flexible interface with the host processor. This paper reports on the design issues and subsequent performance of a soft intellectual property (IP) core implementation of a self-organizing neural network. The design is a development of a previous 0.65- mu m single silicon chip providing an array of 256 neurons, where each neuron stores a 16 element reference vector. Migrating the design to a soft IP core presents challenges in achieving the required performance as regards area, power, and clock speed. This same migration, however, offers opportunities for parameterizing the design in a manner which permits a single soft core to meet the requirements of many end users. Thus, the number of neurons within the single instruction multiple data (SIMD) array, the number of elements per reference vector, and the number of bits of each such element are defined by synthesis time parameters. The construction of the SIMD array of neurons is presented including performance results as regards power, area, and classifications per second . For typical parameters (256 neurons with 16 elements per reference vector) the design provides over 2 000 000 classifications per second using a mainstream 0.18- mu m digital process. A RISC processor, the array controller (AC), provides both the instruction stream and data to the SIMD array of neurons and an interface to a host processor. The design of this processor is discussed with emphasis on the control aspects which permit supply of a continuous instruction stream to the SIMD array and a flexible interface with the host processor. |
| Author | Duncan, A.A. Hendry, D.C. Lightowler, N. |
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| Cites_doi | 10.1109/IJCNN.1999.831063 10.1007/978-3-642-56927-2 10.1016/0167-8191(90)90088-Q 10.4271/2002-01-1109 10.1007/BF00930664 10.1109/IJCNN.1998.682346 10.1016/0141-9331(96)82010-2 10.1109/MM.2002.1013300 10.1109/72.129410 10.4271/2003-01-0359 10.1016/s0141-9331(99)00075-7 10.1016/S0925-2312(98)00042-3 |
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| References | Mann (ref3); 2 Ruping (ref9) 1998; 21 ref12 ref14 Keating (ref18) 1999 ref10 Kohonen (ref1) 2001 Lightowler (ref17) 1997 ref8 Lightowler (ref16) Siemon (ref4); 2 Van den Bout (ref13) 1990 Ienne (ref7) 1996; 13 ref6 Lightowler (ref11) Allen (ref15) Obermayer (ref2) 1990; 13 Hämäläinen (ref5) 1995; 19 |
| References_xml | – volume-title: Modular Maps: An Implementation Strategy for the Self-Organizing Map year: 1997 ident: ref17 – ident: ref12 doi: 10.1109/IJCNN.1999.831063 – volume: 2 start-page: 643 volume-title: Proc. Int. Neural Network Conf. ident: ref4 article-title: Kohonen networks on transputers: Implementation and animation – start-page: 130 volume-title: Proc. WSOM’97 ident: ref11 article-title: A modular approach to implementation of the self-organizing map – start-page: 219 year: 1990 ident: ref13 article-title: Rapid prototyping for neural networks publication-title: Adv. Neural Comput. – year: 2001 ident: ref1 article-title: Self-Organizing Maps doi: 10.1007/978-3-642-56927-2 – volume: 13 start-page: 381 issue: 3 year: 1990 ident: ref2 article-title: Large-scale simulations of self-organizing neural networks on parallel computers: Application to biological modeling publication-title: Parallel Comput. doi: 10.1016/0167-8191(90)90088-Q – year: 1999 ident: ref18 article-title: Reuse Methodology Manual for System-on-a-Chip Designs – volume: 2 start-page: 84 volume-title: Proc. Int. Joint Conf. Neural Networks ident: ref3 article-title: A parallel implementation of Kohonen feature maps on the warp systolic computer – volume-title: SAE World Congress ident: ref15 article-title: Production electro-hydraulic variable valve train for a new generation of I.C. engines doi: 10.4271/2002-01-1109 – volume: 13 start-page: 5 year: 1996 ident: ref7 article-title: Special purpose digital hardware for neural networks: An architectural survey publication-title: J. VLSI Signal Processing Syst. doi: 10.1007/BF00930664 – ident: ref14 doi: 10.1109/IJCNN.1998.682346 – volume: 19 start-page: 447 issue: 8 year: 1995 ident: ref5 article-title: TUTNC: A general purpose parallel computer for neural network computations publication-title: Microprocess. Microsyst. doi: 10.1016/0141-9331(96)82010-2 – ident: ref10 doi: 10.1109/MM.2002.1013300 – ident: ref8 doi: 10.1109/72.129410 – volume-title: SAE World Congress ident: ref16 article-title: Artificial Neural Network Based Control Systems doi: 10.4271/2003-01-0359 – ident: ref6 doi: 10.1016/s0141-9331(99)00075-7 – volume: 21 start-page: 31 year: 1998 ident: ref9 article-title: SOM accelerator system publication-title: Neurocomputing doi: 10.1016/S0925-2312(98)00042-3 |
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| Title | IP core implementation of a self-organizing neural network |
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