APA-Zitierstil (7. Ausg.)

Zhuo, L., Morris, G., & Prasanna, V. (2007). High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. IEEE transactions on parallel and distributed systems, 18(10), 1377-1392. https://doi.org/10.1109/TPDS.2007.1068

Chicago-Zitierstil (17. Ausg.)

Zhuo, Ling, G.R Morris, und V.K Prasanna. "High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs." IEEE Transactions on Parallel and Distributed Systems 18, no. 10 (2007): 1377-1392. https://doi.org/10.1109/TPDS.2007.1068.

MLA-Zitierstil (9. Ausg.)

Zhuo, Ling, et al. "High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs." IEEE Transactions on Parallel and Distributed Systems, vol. 18, no. 10, 2007, pp. 1377-1392, https://doi.org/10.1109/TPDS.2007.1068.