Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework

Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is...

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Veröffentlicht in:	IEEE access Jg. 12; S. 124081 - 124094
Hauptverfasser:	Pudi, Dhilleswararao, Malviya, Shivam, Boppu, Srinivas, Yang, Yu, Hemani, Ahmed, Cenkeramaddi, Linga Reddy
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Piscataway IEEE 2024 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Arrays Binding Coarse-grain reconfigurable architecture Delivery scheduling Distributed management Distributed memory distributed memory architecture Dynamic scheduling dynamically reconfigurable resource array Energy dissipation Fabrics high-level synthesis Image processing Integer linear programming Integer programming Linear algebra Linear programming Mapping Memory management Power demand Power management Radio frequency Random access memory Reconfigurable architectures Reconfiguration Registers Scheduling Switches Task scheduling
ISSN:	2169-3536, 2169-3536
Online-Zugang:	Volltext
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