Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework

Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is...

Full description

Saved in:

Bibliographic Details
Published in:	IEEE access Vol. 12; pp. 124081 - 124094
Main Authors:	Pudi, Dhilleswararao, Malviya, Shivam, Boppu, Srinivas, Yang, Yu, Hemani, Ahmed, Cenkeramaddi, Linga Reddy
Format:	Journal Article
Language:	English
Published:	Piscataway IEEE 2024 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Arrays Binding Coarse-grain reconfigurable architecture Delivery scheduling Distributed management Distributed memory distributed memory architecture Dynamic scheduling dynamically reconfigurable resource array Energy dissipation Fabrics high-level synthesis Image processing Integer linear programming Integer programming Linear algebra Linear programming Mapping Memory management Power demand Power management Radio frequency Random access memory Reconfigurable architectures Reconfiguration Registers Scheduling Switches Task scheduling
ISSN:	2169-3536, 2169-3536
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Abstract	Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is a recently developed VLSI design framework comprising two large-scale reconfigurable fabrics: Dynamically Reconfigurable Resource Array (DRRA) and Distributed Memory Architecture (DiMArch). It uses the Vesyla compiler to map applications on these fabrics. The present version of Vesyla executes binding and scheduling sequentially, with binding first, followed by scheduling. In this paper, we proposed an Integer Linear Programming (ILP)-based exact method to solve scheduling and binding simultaneously that delivers better solutions while mapping applications on these fabrics. The proposed ILP combines two objective functions, one for scheduling and one for binding, and both of these objective functions are coupled with weightage factors <inline-formula> <tex-math notation="LaTeX">\alpha </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">\beta </tex-math></inline-formula> so that the user can have the flexibility to prioritize either scheduling or binding or both based on the requirements. We determined the binding and execution time of image processing tasks and various routines of the Basic Linear Algebraic Subprogram (BLAS) using the proposed ILP for multiple combinations of weightage factors. Furthermore, a comparison analysis has been conducted to compare the latency and power dissipation of several benchmarks between the existing and proposed approaches. The experimental results demonstrate that the proposed method exhibits a substantial reduction in power consumption and latency compared to the existing method.
AbstractList	Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is a recently developed VLSI design framework comprising two large-scale reconfigurable fabrics: Dynamically Reconfigurable Resource Array (DRRA) and Distributed Memory Architecture (DiMArch). It uses the Vesyla compiler to map applications on these fabrics. The present version of Vesyla executes binding and scheduling sequentially, with binding first, followed by scheduling. In this paper, we proposed an Integer Linear Programming (ILP)-based exact method to solve scheduling and binding simultaneously that delivers better solutions while mapping applications on these fabrics. The proposed ILP combines two objective functions, one for scheduling and one for binding, and both of these objective functions are coupled with weightage factors <inline-formula> <tex-math notation="LaTeX">\alpha </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">\beta </tex-math></inline-formula> so that the user can have the flexibility to prioritize either scheduling or binding or both based on the requirements. We determined the binding and execution time of image processing tasks and various routines of the Basic Linear Algebraic Subprogram (BLAS) using the proposed ILP for multiple combinations of weightage factors. Furthermore, a comparison analysis has been conducted to compare the latency and power dissipation of several benchmarks between the existing and proposed approaches. The experimental results demonstrate that the proposed method exhibits a substantial reduction in power consumption and latency compared to the existing method. Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is a recently developed VLSI design framework comprising two large-scale reconfigurable fabrics: Dynamically Reconfigurable Resource Array (DRRA) and Distributed Memory Architecture (DiMArch). It uses the Vesyla compiler to map applications on these fabrics. The present version of Vesyla executes binding and scheduling sequentially, with binding first, followed by scheduling. In this paper, we proposed an Integer Linear Programming (ILP)-based exact method to solve scheduling and binding simultaneously that delivers better solutions while mapping applications on these fabrics. The proposed ILP combines two objective functions, one for scheduling and one for binding, and both of these objective functions are coupled with weightage factors <tex-math notation="LaTeX">$\alpha $ </tex-math> and <tex-math notation="LaTeX">$\beta $ </tex-math> so that the user can have the flexibility to prioritize either scheduling or binding or both based on the requirements. We determined the binding and execution time of image processing tasks and various routines of the Basic Linear Algebraic Subprogram (BLAS) using the proposed ILP for multiple combinations of weightage factors. Furthermore, a comparison analysis has been conducted to compare the latency and power dissipation of several benchmarks between the existing and proposed approaches. The experimental results demonstrate that the proposed method exhibits a substantial reduction in power consumption and latency compared to the existing method. Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is a recently developed VLSI design framework comprising two large-scale reconfigurable fabrics: Dynamically Reconfigurable Resource Array (DRRA) and Distributed Memory Architecture (DiMArch). It uses the Vesyla compiler to map applications on these fabrics. The present version of Vesyla executes binding and scheduling sequentially, with binding first, followed by scheduling. In this paper, we proposed an Integer Linear Programming (ILP)-based exact method to solve scheduling and binding simultaneously that delivers better solutions while mapping applications on these fabrics. The proposed ILP combines two objective functions, one for scheduling and one for binding, and both of these objective functions are coupled with weightage factors $\alpha $ and $\beta $ so that the user can have the flexibility to prioritize either scheduling or binding or both based on the requirements. We determined the binding and execution time of image processing tasks and various routines of the Basic Linear Algebraic Subprogram (BLAS) using the proposed ILP for multiple combinations of weightage factors. Furthermore, a comparison analysis has been conducted to compare the latency and power dissipation of several benchmarks between the existing and proposed approaches. The experimental results demonstrate that the proposed method exhibits a substantial reduction in power consumption and latency compared to the existing method. Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is a recently developed VLSI design framework comprising two large-scale reconfigurable fabrics: Dynamically Reconfigurable Resource Array (DRRA) and Distributed Memory Architecture (DiMArch). It uses the Vesyla compiler to map applications on these fabrics. The present version of Vesyla executes binding and scheduling sequentially, with binding first, followed by scheduling. In this paper, we proposed an Integer Linear Programming (ILP)-based exact method to solve scheduling and binding simultaneously that delivers better solutions while mapping applications on these fabrics. The proposed ILP combines two objective functions, one for scheduling and one for binding, and both of these objective functions are coupled with weightage factors [Formula Omitted] and [Formula Omitted] so that the user can have the flexibility to prioritize either scheduling or binding or both based on the requirements. We determined the binding and execution time of image processing tasks and various routines of the Basic Linear Algebraic Subprogram (BLAS) using the proposed ILP for multiple combinations of weightage factors. Furthermore, a comparison analysis has been conducted to compare the latency and power dissipation of several benchmarks between the existing and proposed approaches. The experimental results demonstrate that the proposed method exhibits a substantial reduction in power consumption and latency compared to the existing method.
Author	Boppu, Srinivas Pudi, Dhilleswararao Yang, Yu Hemani, Ahmed Cenkeramaddi, Linga Reddy Malviya, Shivam
Author_xml	– sequence: 1 givenname: Dhilleswararao orcidid: 0000-0001-7054-0254 surname: Pudi fullname: Pudi, Dhilleswararao organization: School of Electrical Sciences, Indian Institute of Technology at Bhubaneswar, Bhubaneswar, India – sequence: 2 givenname: Shivam orcidid: 0009-0003-4176-121X surname: Malviya fullname: Malviya, Shivam organization: School of Electrical Sciences, Indian Institute of Technology at Bhubaneswar, Bhubaneswar, India – sequence: 3 givenname: Srinivas orcidid: 0000-0001-9028-2563 surname: Boppu fullname: Boppu, Srinivas organization: School of Electrical Sciences, Indian Institute of Technology at Bhubaneswar, Bhubaneswar, India – sequence: 4 givenname: Yu orcidid: 0000-0003-2396-3590 surname: Yang fullname: Yang, Yu organization: Division of Electronics and Embedded Systems, KTH Royal Institute of Technology, Stockholm, Sweden – sequence: 5 givenname: Ahmed orcidid: 0000-0003-0565-9376 surname: Hemani fullname: Hemani, Ahmed organization: Division of Electronics and Embedded Systems, KTH Royal Institute of Technology, Stockholm, Sweden – sequence: 6 givenname: Linga Reddy orcidid: 0000-0002-1023-2118 surname: Cenkeramaddi fullname: Cenkeramaddi, Linga Reddy email: linga.cenkeramaddi@uia.no organization: Department of ICT, University of Agder, Grimstad, Norway
BackLink	https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-354595$$DView record from Swedish Publication Index (Kungliga Tekniska Högskolan)
BookMark	eNp9kU9r3DAQxU1JIWmaT5AeDD17q_-2jptt0i4stLBJoSchyWNHG6-0lWxCvn21cQppD5UOM4ze7zHivStOfPBQFJcYLTBG8tNytbrebhcEEbagjFOO6JvijGAhK8qpOHnVnxYXKe1QPk0e8fqs-Ln2I_QQy43zoGP5PYY-6v3e-b660gnacuv20zBqD2FK5dbeQzsN-bXUvi2vnG-PfRdi1m10H8qbTMNjiA_vi7edHhJcvNTz4u7m-nb1tdp8-7JeLTeVZaweK0Yt0l2-woIAQ4joOgIoF6utsI1tG2aY5dLWxCKEa0wQ7gznUjSmRR09L9azbxv0Th2i2-v4pIJ26nkQYq90HJ0dQEkEiCNjmGkks8Y0JHtyCUJYVjPWZq9q9kqPcJjMX26f3Y_ls9vDeK8oZ1zyrP846w8x_JogjWoXpujzdxXFiEgha0GySs4qG0NKETpl3ahHF_wYtRsURuoYpJqDVMcg1UuQmaX_sH92-j_1YaYcALwihKCUNfQ3HD2r_A
CODEN	IAECCG
CitedBy_id	crossref_primary_10_1109_ACCESS_2024_3484175 crossref_primary_10_1016_j_compeleceng_2025_110104
Cites_doi	10.1109/NORCHIP.2010.5669436 10.1109/VLSID57277.2023.00020 10.1007/978-3-319-31596-6_3 10.1145/1508128.1508158 10.1109/ISVLSI.2019.00106 10.1109/ASICON.2009.5351593 10.1145/3061639.3062262 10.1145/3597031.3597049 10.1145/2463209.2488756 10.1145/3431920.3439292 10.1109/PATMOS.2016.7833431 10.1109/DATE.2001.915091 10.1109/DSD60849.2023.00013 10.1109/TCAD.2010.2098571 10.1145/996566.996685 10.1145/3503222.3507772 10.1109/ISVLSI.2017.15 10.1007/s11265-017-1326-7 10.1109/FPL.2006.311262 10.1109/MICRO.1994.717412 10.1109/SBCCI60457.2023.10261953 10.1109/DSD53832.2021.00044 10.1109/DAC.2018.8465799 10.1109/VLSID.2011.54 10.1145/3229631.3229650 10.1007/BF02575586 10.1109/ASAP.2017.7995277 10.1109/4.121562 10.1109/DASIP.2010.5706261 10.1109/IPDPSW55747.2022.00112 10.1016/j.disopt.2017.12.001 10.1145/2228360.2228600 10.1109/TCAD.2021.3132551 10.1016/j.scs.2019.101523 10.1109/CGO.2004.1281665 10.1007/s10617-024-09286-y
ContentType	Journal Article
Copyright	Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024
Copyright_xml	– notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024
DBID	97E ESBDL RIA RIE AAYXX CITATION 7SC 7SP 7SR 8BQ 8FD JG9 JQ2 L7M L~C L~D ADTPV AFDQA AOWAS D8T D8V ZZAVC DOA
DOI	10.1109/ACCESS.2024.3453503
DatabaseName	IEEE All-Society Periodicals Package (ASPP) 2005–Present IEEE Xplore Open Access Journals IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE/IET Electronic Library CrossRef Computer and Information Systems Abstracts Electronics & Communications Abstracts Engineered Materials Abstracts METADEX Technology Research Database Materials Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional SwePub SWEPUB Kungliga Tekniska Högskolan full text SwePub Articles SWEPUB Freely available online SWEPUB Kungliga Tekniska Högskolan SwePub Articles full text DOAJ Directory of Open Access Journals
DatabaseTitle	CrossRef Materials Research Database Engineered Materials Abstracts Technology Research Database Computer and Information Systems Abstracts – Academic Electronics & Communications Abstracts ProQuest Computer Science Collection Computer and Information Systems Abstracts Advanced Technologies Database with Aerospace METADEX Computer and Information Systems Abstracts Professional
DatabaseTitleList	Materials Research Database
Database_xml	– sequence: 1 dbid: DOA name: DOAJ Directory of Open Access Journals url: https://www.doaj.org/ sourceTypes: Open Website – sequence: 2 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher
DeliveryMethod	fulltext_linktorsrc
Discipline	Engineering
EISSN	2169-3536
EndPage	124094
ExternalDocumentID	oai_doaj_org_article_90e050bb4b894cbb8272c59e66c4744d oai_DiVA_org_kth_354595 10_1109_ACCESS_2024_3453503 10663348
Genre	orig-research
GrantInformation_xml	– fundername: Indo-Norwegian Collaboration in Autonomous Cyber-Physical Systems (INCAPS) through the International Partnerships for Excellent Education, Research and Innovation (INTPART) Program from the Research Council of Norway grantid: 287918
GroupedDBID	0R~ 4.4 5VS 6IK 97E AAJGR ABAZT ABVLG ACGFS ADBBV AGSQL ALMA_UNASSIGNED_HOLDINGS BCNDV BEFXN BFFAM BGNUA BKEBE BPEOZ EBS EJD ESBDL GROUPED_DOAJ IPLJI JAVBF KQ8 M43 M~E O9- OCL OK1 RIA RIE RNS AAYXX CITATION 7SC 7SP 7SR 8BQ 8FD JG9 JQ2 L7M L~C L~D ADTPV AFDQA AOWAS D8T D8V ZZAVC
ID	FETCH-LOGICAL-c447t-43c0afafa6ce6eb226ff2e026fcac6c8cd84b4c59c72c00171201fb55968bd0f3
IEDL.DBID	RIE
ISICitedReferencesCount	2
ISICitedReferencesURI	http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=001311208000001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN	2169-3536
IngestDate	Fri Oct 03 12:34:40 EDT 2025 Tue Nov 04 16:57:42 EST 2025 Mon Jun 30 16:34:03 EDT 2025 Sat Nov 29 04:27:04 EST 2025 Tue Nov 18 21:49:03 EST 2025 Wed Aug 27 02:00:19 EDT 2025
IsDoiOpenAccess	true
IsOpenAccess	true
IsPeerReviewed	true
IsScholarly	true
Language	English
License	https://creativecommons.org/licenses/by-nc-nd/4.0
LinkModel	DirectLink
MergedId	FETCHMERGED-LOGICAL-c447t-43c0afafa6ce6eb226ff2e026fcac6c8cd84b4c59c72c00171201fb55968bd0f3
Notes	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ORCID	0000-0001-9028-2563 0000-0003-2396-3590 0000-0003-0565-9376 0009-0003-4176-121X 0000-0001-7054-0254 0000-0002-1023-2118
OpenAccessLink	https://ieeexplore.ieee.org/document/10663348
PQID	3102969762
PQPubID	4845423
PageCount	14
ParticipantIDs	crossref_citationtrail_10_1109_ACCESS_2024_3453503 swepub_primary_oai_DiVA_org_kth_354595 doaj_primary_oai_doaj_org_article_90e050bb4b894cbb8272c59e66c4744d crossref_primary_10_1109_ACCESS_2024_3453503 proquest_journals_3102969762 ieee_primary_10663348
PublicationCentury	2000
PublicationDate	20240000 2024-00-00 20240101 2024 2024-01-01
PublicationDateYYYYMMDD	2024-01-01
PublicationDate_xml	– year: 2024 text: 20240000
PublicationDecade	2020
PublicationPlace	Piscataway
PublicationPlace_xml	– name: Piscataway
PublicationTitle	IEEE access
PublicationTitleAbbrev	Access
PublicationYear	2024
Publisher	IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher_xml	– name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
References	ref35 ref12 ref34 ref15 ref37 ref14 ref36 ref31 ref30 ref33 ref10 ref32 ref2 ref17 ref39 ref16 ref38 ref19 ref18 Shami (ref11) 2012 Yang (ref13) 2022 Nickel (ref43) 2021 Johnson (ref42) 1979 Kim (ref1) ref24 ref23 ref26 ref25 ref20 ref41 ref22 ref21 ref28 ref29 ref7 ref9 ref4 ref6 ref5 ref40 Lai (ref3) Park (ref27) Min-Allah (ref8) 2019; 48
References_xml	– ident: ref16 doi: 10.1109/NORCHIP.2010.5669436 – year: 2012 ident: ref11 article-title: Dynamically reconfigurable resource array – ident: ref21 doi: 10.1109/VLSID57277.2023.00020 – start-page: 166 volume-title: Proc. Int. Conf. Parallel Archit. Compilation Techn. ident: ref27 article-title: Edge-centric modulo scheduling for coarse-grained reconfigurable architectures – ident: ref10 doi: 10.1007/978-3-319-31596-6_3 – ident: ref26 doi: 10.1145/1508128.1508158 – ident: ref20 doi: 10.1109/ISVLSI.2019.00106 – ident: ref17 doi: 10.1109/ASICON.2009.5351593 – ident: ref36 doi: 10.1145/3061639.3062262 – ident: ref22 doi: 10.1145/3597031.3597049 – year: 2022 ident: ref13 article-title: Vesyla-II: An algorithm library development tool for synchoros VLSI design style publication-title: arXiv:2206.07984 – ident: ref29 doi: 10.1145/2463209.2488756 – ident: ref4 doi: 10.1145/3431920.3439292 – ident: ref12 doi: 10.1109/PATMOS.2016.7833431 – ident: ref6 doi: 10.1109/DATE.2001.915091 – ident: ref24 doi: 10.1109/DSD60849.2023.00013 – ident: ref25 doi: 10.1109/TCAD.2010.2098571 – ident: ref5 doi: 10.1145/996566.996685 – ident: ref41 doi: 10.1145/3503222.3507772 – start-page: 826 volume-title: Proc. 46th ACM/IEEE Design Autom. Conf. ident: ref1 article-title: Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems – ident: ref9 doi: 10.1109/ISVLSI.2017.15 – start-page: 9 volume-title: IBM ILOG CPLEX Optimization Studio year: 2021 ident: ref43 – ident: ref15 doi: 10.1007/s11265-017-1326-7 – ident: ref32 doi: 10.1109/FPL.2006.311262 – ident: ref30 doi: 10.1109/MICRO.1994.717412 – ident: ref23 doi: 10.1109/SBCCI60457.2023.10261953 – volume-title: Computers and Intractability: A Guide to the Theory of NP-Completeness year: 1979 ident: ref42 – ident: ref35 doi: 10.1109/DSD53832.2021.00044 – ident: ref37 doi: 10.1109/DAC.2018.8465799 – ident: ref14 doi: 10.1109/VLSID.2011.54 – ident: ref18 doi: 10.1145/3229631.3229650 – ident: ref31 doi: 10.1007/BF02575586 – ident: ref2 doi: 10.1109/ASAP.2017.7995277 – ident: ref34 doi: 10.1109/4.121562 – ident: ref33 doi: 10.1109/DASIP.2010.5706261 – ident: ref40 doi: 10.1109/IPDPSW55747.2022.00112 – ident: ref7 doi: 10.1016/j.disopt.2017.12.001 – ident: ref28 doi: 10.1145/2228360.2228600 – ident: ref39 doi: 10.1109/TCAD.2021.3132551 – volume: 48 year: 2019 ident: ref8 article-title: Cost efficient resource allocation for real-time tasks in embedded systems publication-title: Sustain. Cities Soc. doi: 10.1016/j.scs.2019.101523 – ident: ref38 doi: 10.1109/CGO.2004.1281665 – start-page: 1 volume-title: Proc. 39th IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD) ident: ref3 article-title: SuSy: A programming model for productive construction of high-performance systolic arrays on FPGAs – ident: ref19 doi: 10.1007/s10617-024-09286-y
SSID	ssj0000816957
Score	2.3131359
Snippet	Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications...
SourceID	doaj swepub proquest crossref ieee
SourceType	Open Website Open Access Repository Aggregation Database Enrichment Source Index Database Publisher
StartPage	124081
SubjectTerms	Arrays Binding Coarse-grain reconfigurable architecture Delivery scheduling Distributed management Distributed memory distributed memory architecture Dynamic scheduling dynamically reconfigurable resource array Energy dissipation Fabrics high-level synthesis Image processing Integer linear programming Integer programming Linear algebra Linear programming Mapping Memory management Power demand Power management Radio frequency Random access memory Reconfigurable architectures Reconfiguration Registers Scheduling Switches Task scheduling
SummonAdditionalLinks	– databaseName: DOAJ Directory of Open Access Journals dbid: DOA link: http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwrV1LT9wwEB4hxAEOqOUhQmnlQ9UTAW_i53F36YoDQkg8BCfLcZxlBYRq2fL7GTteFC70UuWWOHIy3zjzjTX5BuCnx2zNIY3NkSuLnDXoxqrBdWVLZKfCSypim86bM3l-rm5v9UWv1VeoCevkgTvDHWvqKadVxSqlmasqVcjCce2FcEwyVoevL5W6l0zFb7AaCM1lkhkaUH08HI_xjTAhLNhRyXjJl22yUiiKiv2pxcpHttlXEI1RZ_IFNhNdJMPuMb_Cim-3YKMnIrgNd2FTb-rnBNNKdFty0VVcPeHFfIQxqiaXs1A2aFuPWT65RJTqUH4-JbatyWgWf2shyF1x3JmdPpPJsl5rB64nv6_Gp3lqmJA7xuQiZ6WjtsFDOC8QhEI0TeExy2qcdcIpVytWMbSeQxtGpRwM_02FSYVQVU2bchdW2-fW7wGxlmPoRrwkr5lWzEo7UJbj6tWIJ7cZFEvbGZfUxENTi0cTswqqTWdwEwxuksEzOHy_6U8npvH58FEA5X1oUMKOJ9A_TPIP8y__yGAnQNqbDzlWyVQGB0uMTVq2Lwa5bqEFMrQig18d7h9mP5ndDOPsD4t7UyL51Hz_fzzkN1gPL95t7RzA6mL-13-HNfe6mL3Mf0TXfgNCW_kf priority: 102 providerName: Directory of Open Access Journals
Title	Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework
URI	https://ieeexplore.ieee.org/document/10663348 https://www.proquest.com/docview/3102969762 https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-354595 https://doaj.org/article/90e050bb4b894cbb8272c59e66c4744d
Volume	12
WOSCitedRecordID	wos001311208000001&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText	1
inHoldings	1
isFullTextHit
isPrint
journalDatabaseRights	– providerCode: PRVAON databaseName: DOAJ Directory of Open Access Journals customDbUrl: eissn: 2169-3536 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0000816957 issn: 2169-3536 databaseCode: DOA dateStart: 20130101 isFulltext: true titleUrlDefault: https://www.doaj.org/ providerName: Directory of Open Access Journals – providerCode: PRVHPJ databaseName: ROAD: Directory of Open Access Scholarly Resources customDbUrl: eissn: 2169-3536 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0000816957 issn: 2169-3536 databaseCode: M~E dateStart: 20130101 isFulltext: true titleUrlDefault: https://road.issn.org providerName: ISSN International Centre
link	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LT9tAEB6VqAc4UFpAmALaA-JUg7H3eUxSoh4oQqJFcFqt1-sQAQ7KgyO_vbPrTRQOrVRFsqJ4nfX6m9F8M56dATh26K1ZpLEpcmWe0hrFWNaoV6ZAdsqdyHho03l7Ka6u5N2duo6b1cNeGOdcSD5zp_5reJdfje3ch8pQw9E-FlSuwZoQvN2stQyo-A4SiolYWeg8U2fdfh8XgT5gTk8Lygq26IwVrU8o0h-7qrwnmKtFQ4OhGXz6z1vcgs3IKEm3FYHP8ME1X2Bjpc7gNtz7uN_QTQh6nijZ5LpNynrGk2kPzVhFbkY-s9A0bjyfkhsEsvIZ6kNimor0RmHnC0F6i-MuzXBMBouUrh34Pbj41f-Rxp4KqaVUzFJa2MzU-OHWccQp53WdO3TEamsst9JWkpbUMmVFbkMxHWQIdYl-B5dlldXFLnSaceP2gBjD0LojpIJVVElqhDmXhqGCK4ScmQTyxbPWNhYc930vnnRwPDKlW4C0B0hHgBL4trzopa238e_hPQ_icqgvlh1-QFB01D2tMpexrCxpKRW1ZSlzXBtTjnNLBaVVAjseyJX5WgwTOFjIhI6aPdVIh3PFkcTlCZy0cvJu9u-j226Y_XH2oAvkp4rt_-X_v8K6X0sb0DmAzmwyd4fw0b7ORtPJUYgO4PHn28VRkPQ_CI75JQ
linkProvider	IEEE
linkToHtml	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3db9MwED_BQAIe-BxaxgA_IJ7I5jm2Yz-2hWqIUk3amMaT5ThOqdjSqR_8_Ts7btU9gIT6EjVOHOd3p_vd5XwH8MGjt-aQxubIlWXOGxRj1aBe2QLZqfQllbFN58WoHI_V5aU-TZvV414Y731MPvOH4TB-y69nbhVCZajhaB8Lru7DA8E5o912rU1IJfSQ0KJMtYWOqT7qDQa4DPQCGT8suCjEujdWsj-xTH_qq3KXYm6XDY2mZvjsPx_yOTxNnJL0OiF4Afd8-xKebFUafAU_Q-Rv4ucEfU-UbXLapWVd48m8j4asJmfTkFtoWz9bLcgZQlmHHPUJsW1N-tO494UgwcVxIzuZkeE6qWsXfgy_nA9O8tRVIXecl8ucF47aBn_SeYlIMdk0zKMr1jjrpFOuVrziTmhXMhfL6SBHaCr0PKSqatoUr2GnnbV-D4i1Au07glqKmmvFbWmPlRWo4hpBFzYDtn7XxqWS46HzxZWJrgfVpgPIBIBMAiiDT5uLbrqKG_8e3g8gboaGctnxDwTFJO0zmnoqaFXxSmnuqkoxXJvQXkrHS87rDHYDkFvzdRhmcLCWCZN0e2GQEDMtkcaxDD52cnJn9s_Ti16c_ffylymQoWqx_5f7v4dHJ-ffR2b0dfztDTwO6-rCOwews5yv_Ft46P4sp4v5uyjpt2DS-kY
openUrl	ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Integer+Linear+Programming-Based+Simultaneous+Scheduling+and+Binding+for+SiLago+Framework&rft.jtitle=IEEE+access&rft.au=Pudi%2C+Dhilleswararao&rft.au=Malviya%2C+Shivam&rft.au=Boppu%2C+Srinivas&rft.au=Yu%2C+Yang&rft.date=2024&rft.issn=2169-3536&rft.eissn=2169-3536&rft.volume=12&rft.spage=124081&rft_id=info:doi/10.1109%2FACCESS.2024.3453503&rft.externalDocID=oai_DiVA_org_kth_354595
thumbnail_l	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=2169-3536&client=summon
thumbnail_m	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=2169-3536&client=summon
thumbnail_s	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=2169-3536&client=summon