Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based...

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Vydáno v:	IEEE transactions on signal processing Ročník 52; číslo 5; s. 1315 - 1326
Hlavní autoři:	Hongyu Liao, Mandal, M.Kr, Cockburn, B.F.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York, NY IEEE 01.05.2004 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Applied sciences Architecture Arrays Buffers Clocks Computational complexity Computer architecture Discrete wavelet transforms Exact sciences and technology Filters Hardware Hoisting Information, signal and communications theory Interleaved codes Recursive Signal and communications theory Signal representation. Spectral analysis Signal, noise Studies Telecommunications and information theory Two dimensional displays Utilization Wavelet Wavelet coefficients Wavelet transforms Discrete wavelet transform recursive architecture Data processing Two dimensional model Buffer memory Buffer system Discrete wavelet transforms Clock Computational complexity Implementation lifting scheme Wavelets Wavelet transformation Recursive method Signal processing dual scan architecture Signal analysis
ISSN:	1053-587X, 1941-0476
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Shrnutí:	The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional (2-D) versions of what we call recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a five-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The recursive and dual scan architectures can be readily extended to the 2-D case. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures.
Bibliografie:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 ObjectType-Article-1 ObjectType-Feature-2 content type line 23
ISSN:	1053-587X 1941-0476
DOI:	10.1109/TSP.2004.826175