A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing

Stochastic computing (SC) has been applied on the implementations of complex arithmetic functions. Complicated polynomial-based approximations lead to large hardware complexity of previous SC circuits for arithmetic functions. In this paper, a novel piecewise approximation method based on Taylor ser...

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Vydané v:IEEE access Ročník 8; s. 1
Hlavní autori: Qin, Zidi, Qiu, Yuou, Zheng, Muhan, Dong, Hongxi, Lu, Zhonghai, Wang, Zhongfeng, Pan, Hongbing
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Piscataway IEEE 01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Approximation
Approximation methods
Arithmetic
arithmetic functions
Circuits
Complexity
Complexity theory
Computation
Computer architecture
Critical path
Functions (mathematics)
Hardware
Indexes
Logic gates
Mathematical analysis
Mathematical functions
Optimization
Polynomials
Series expansion
Stochastic computing
Taylor series
VLSI architecture
ISSN:2169-3536, 2169-3536
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Popis
Shrnutí:Stochastic computing (SC) has been applied on the implementations of complex arithmetic functions. Complicated polynomial-based approximations lead to large hardware complexity of previous SC circuits for arithmetic functions. In this paper, a novel piecewise approximation method based on Taylor series expansion is proposed for complex arithmetic functions. Efficient implementations based on unipolar stochastic logic are presented for the monotonic functions. Furthermore, detailed optimization schemes are provided for the non-monotonic functions. Using NAND and AND gates as main computing elements, the optimized hardware architectures have extremely low complexity. The experimental results show that a broad range of arithmetic functions can be implemented with the proposed SC circuits, and the mean absolute errors can achieve the order of 1 × 10-3. Compared with the state-of-the-art works, the approximation precision for some typical functions can be increased by more than 8× with our method. In addition, the proposed circuits outperform the previous methods in hardware complexity and critical path significantly.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2020.2978399