Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test

Rapid developments in semiconductor technology have substantially increased the computational capability of computers. As a result of this and recent developments in theory, machine learning (ML) techniques have become attractive in many new applications. This trend has also inspired researchers wor...

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Vydáno v:Integration (Amsterdam) Ročník 77; s. 113 - 130
Hlavní autoři: Afacan, Engin, Lourenço, Nuno, Martins, Ricardo, Dündar, Günhan
Médium: Journal Article
Jazyk:angličtina
Vydáno: Elsevier B.V 01.03.2021
Elsevier
Témata:
Analog and radio frequency
Artificial intelligence
Artificial neural network
Deep learning
Engineering Sciences
Integrated circuits
Machine learning
Optimization
Synthesis
Analog and radio frequency
Deep learning
Integrated circuits
Synthesis
Machine learning
Artificial neural network
Artificial intelligence
Optimization
ISSN:0167-9260, 1872-7522
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Shrnutí:Rapid developments in semiconductor technology have substantially increased the computational capability of computers. As a result of this and recent developments in theory, machine learning (ML) techniques have become attractive in many new applications. This trend has also inspired researchers working on integrated circuit (IC) design and optimization. ML-based design approaches have gained importance to challenge/aid conventional design methods since they can be employed at different design levels, from modeling to test, to learn any nonlinear input-output relationship of any analog and radio frequency (RF) device or circuit; thus, providing fast and accurate responses to the task that they have learned. Furthermore, employment of ML techniques in analog/RF electronic design automation (EDA) tools boosts the performance of such tools. In this paper, we summarize the recent research and present a comprehensive review on ML techniques for analog/RF circuit modeling, design, synthesis, layout, and test.
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2020.11.006