Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

Information security is essential to ensure security of exchanged sensitive data in resource‐constrained devices (RCDs) because they are used widely in the Internet of things (IoT). The implementation of special ciphers is required in these RCDs, as they have many limitations and constraints, such a...

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Vydané v:IET circuits, devices & systems Ročník 15; číslo 2; s. 121 - 135
Hlavní autori: Abed, Sa'ed, Jaffal, Reem, Mohd, Bassam Jamil, Alshayeji, Mohammad
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Stevenage John Wiley & Sons, Inc 01.03.2021
Wiley
Predmet:
Access control
Algorithms
Business metrics
Circuit design
Cryptography
Cybersecurity
Design
Digital integrated circuits
Encryption
Energy consumption
Energy dissipation
Field programmable gate arrays
Hardware
Internet of Things
Performance evaluation
Performance measurement
Power management
Security management
security of data
ISSN:1751-858X, 1751-8598
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Shrnutí:Information security is essential to ensure security of exchanged sensitive data in resource‐constrained devices (RCDs) because they are used widely in the Internet of things (IoT). The implementation of special ciphers is required in these RCDs, as they have many limitations and constraints, such as low power/energy dissipation, and require low hardware resources. The SM4 cipher is one of the common block ciphers, which can be easily implemented and offers a high level of security. The objective of this study is to determine the optimum field‐programmable gate array (FPGA) design for SM4 to facilitate reconfiguring the FPGA with an optimum design during operation. Various FPGA design options for SM4 ciphers are examined, and the performance metrics are modeled: power, energy, area, and speed. Scalar and pipelined designs with one or multiple hardware rounds are considered without altering the cipher algorithm. The results show that the best scalar implementation utilises less resources than the pipelined implementations by 7%. Alternatively, pipelined implementations perform better regarding speed and energy dissipation by 10 times and 40% of the scalar implementation, respectively. The pipeline implementations with eight or 16 rounds are optimum for continuous streams of data, and the two‐round design is the optimum design across ciphers.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:1751-858X
1751-8598
DOI:10.1049/cds2.12011