Networked Power-Gated MRAMs for Memory-Based Computing

Emerging nonvolatile memory technologies open new perspectives for original computing architectures. In this paper, we propose a new type of flexible and energy-efficient architecture that relies on power-gated distributed magnetoresistive random access memory (MRAM). The proposed architecture uses...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems Jg. 26; H. 12; S. 2696 - 2708
Hauptverfasser: Diguet, Jean-Philippe, Onizawa, Naoya, Rizk, Mostafa, Sepulveda, Johanna, Baghdadi, Amer, Hanyu, Takahiro
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.12.2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Bandwidth
Computation
Computer architecture
Computer Arithmetic
Computer memory
Computer Science
Computer simulation
Distributed memory
Distributed, Parallel, and Cluster Computing
Electric power distribution
Electronics
Embedded Systems
Energy management
Engineering Sciences
Information Theory
magnetoresistive random access memory (MRAM)
Magnetoresistivity
Micro and nanotechnologies
Microelectronics
Microprocessors
network-on-chip (NoC)
Networking and Internet Architecture
Neural networks
Nonvolatile memory
power gating (PG)
Power management
Random access memory
Reduction
Search engines
Signal and Image Processing
sparse neural networks (SNNs)
Static random access memory
System on chip
Sparse-neural networks
NOC
Index Terms-MRAM
MRAM
Database
Sparse- neural networks
Power-gating
ISSN:1063-8210, 1557-9999
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Emerging nonvolatile memory technologies open new perspectives for original computing architectures. In this paper, we propose a new type of flexible and energy-efficient architecture that relies on power-gated distributed magnetoresistive random access memory (MRAM). The proposed architecture uses a network-on-chip (NoC) to interconnect MRAM-based clusters, processing elements, and managers. The NoC distributes application-specific commands to MRAM devices by means of packets. Configurable network interfaces allow to transform MRAM devices into smart units able to respond to incoming commands. In this context, three types of MRAM designs are proposed with different power-gating policies and granularities. A relevant database search engine case study is considered to illustrate the benefits of this proposed architecture. It is implemented with a sparse-neural-network approach and simulated in SystemC with different scenarios including hundreds of database queries. Hardware designs and accurate power estimations have been conducted. The obtained results demonstrate important power reduction with database hit rates of about 94%. Targeting 65-nm technology, energy savings reach 87% when compared with an static random access memory-based implementation. Moreover, a new asymmetric read/write MRAM type provides from 39% to 50% energy reduction with respect to the other fixed-granularity models. This results in a low-power, highly scalable, and configurable implementation of memory-based computing.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2018.2856458