LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems Vol. 42; no. 6; pp. 2069 - 2073
Main Authors: Yan, Aibin, Li, Zhixing, Cui, Jie, Huang, Zhengfeng, Ni, Tianming, Girard, Patrick, Wen, Xiaoqing
Format: Journal Article
Language:English
Published: New York IEEE 01.06.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithm-based verification
Algorithms
Electronic design automation
Engineering Sciences
Error recovery
fault tolerance
Feedback loop
Feedback loops
Feeds
Integrated circuits
Inverters
latch design
Latches
Micro and nanotechnologies
Microelectronics
Muller C-element (MCE)
multiple-node-upset (MNU)
Nodes
Recovery
Switching circuits
Transistors
Verification
Fault tolerance
Algorithm-based verification
Multiple-node-upset
Muller C-element
Latch design
ISSN:0278-0070, 1937-4151
Online Access:Get full text
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Summary:In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this article, a latch design protected against MNUs in the harsh radiation as well as an algorithm-based verification process is proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2022.3213212