Integer Linear Programming Models for Global Routing
Modern integrated circuit design involves the layout of circuits consisting of millions of switching elements or transistors. Due to the sheer complexity of the problem, optimizing the connectivity between transistors is very difficult. The circuit interconnection is the single most important factor...
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| Published in: | INFORMS journal on computing Vol. 18; no. 2; pp. 137 - 150 |
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| Main Authors: | , , |
| Format: | Journal Article |
| Language: | English |
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Linthicum
INFORMS
22.03.2006
Institute for Operations Research and the Management Sciences |
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| ISSN: | 1091-9856, 1526-5528, 1091-9856 |
| Online Access: | Get full text |
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| Abstract | Modern integrated circuit design involves the layout of circuits consisting of millions of switching elements or transistors. Due to the sheer complexity of the problem, optimizing the connectivity between transistors is very difficult. The circuit interconnection is the single most important factor in performance criteria such as signal delay, power dissipation, circuit size, and cost. These factors dictate that interconnections, i.e., wires, be made as short as possible. The wire-minimization problem is generally formulated as a sequence of discrete optimization subproblems that are known to be NP-hard. Hence, they can only be solved approximately using meta-heuristics. These methods are computationally expensive and the quality of the solution depends to a great extent on an appropriate choice of starting configuration and modeling techniques. In this paper, new modeling techniques are used to solve the routing problem formulated as an integer programming problem. The main contribution of this paper is a proposed global routing heuristic that combines the wire length, channel congestion, and number of pins in routes to find the best wiring layout of a circuit. By adding information such as channel congestion and the number of pins in each route as well as the wire length, the quality of the solution is improved. In addition, the solutions of the large relaxed linear programming problems are skewed towards a zero-one solution, resulting in faster convergence. The developed LP models in this paper are useful when solving the global routing problem for two reasons; first, the new interior-point algorithms to solve the LP problem are polynomial in time. Second, "near optimal wiring" is obtained in polynomial time without performing randomized rounding. |
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| AbstractList | Modern integrated circuit design involves the layout of circuits consisting of millions of switching elements or transistors. Due to the sheer complexity of the problem, optimizing the connectivity between transistors is very difficult. The circuit interconnection is the single most important factor in performance criteria such as signal delay, power dissipation, circuit size, and cost. These factors dictate that interconnections, i.e., wires, be made as short as possible. The wire-minimization problem is generally formulated as a sequence of discrete optimization subproblems that are known to be NP-hard. Hence, they can only be solved approximately using meta-heuristics. These methods are computationally expensive and the quality of the solution depends to a great extent on an appropriate choice of starting configuration and modeling techniques. In this paper, new modeling techniques are used to solve the routing problem formulated as an integer programming problem. The main contribution of this paper is a proposed global routing heuristic that combines the wire length, channel congestion, and number of pins in routes to find the best wiring layout of a circuit. By adding information such as channel congestion and the number of pins in each route as well as the wire length, the quality of the solution is improved. In addition, the solutions of the large relaxed linear programming problems are skewed towards a zero-one solution, resulting in faster convergence. The developed LP models in this paper are useful when solving the global routing problem for two reasons; first, the new interior-point algorithms to solve the LP problem are polynomial in time. Second, “near optimal wiring” is obtained in polynomial time without performing randomized rounding. Modern integrated circuit design involves the layout of circuits consisting of millions of switching elements or transistors. The circuit interconnection is the single most important factor in performance criteria such as signal delay, power dissipation, circuit size, and cost. Due to the sheer complexity of the problem, optimizing the connectivity between transistors is very difficult. In this paper, new modeling techniques are used to solve the routing problem formulated as an integer programming problem. The main contribution of this paper is a proposed global muting heuristic that combines the wire length, channel congestion, and number of pins in routes to find the best wiring layout of a circuit. The developed linear programming (LP) models in this paper are useful when solving the global routing problem for two reasons; first, the new interior-point algorithms to solve the LP problem are polynomial in time. Second, "near optimal wiring" is obtained in polynomial time without performing randomized rounding. |
| Audience | Academic |
| Author | Vannelli, Anthony Behjat, Laleh Rosehart, William |
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| Cites_doi | 10.1109/43.331403 10.1109/43.602477 10.1145/369691.369699 10.1007/BFb0121044 10.1007/978-3-322-92106-2 10.1137/0802028 10.1109/TCAD.2002.801083 10.1109/TEC.1961.5219222 10.1109/43.68406 10.1007/978-1-4684-2001-2_9 10.1137/0204019 10.1137/0114025 10.1109/TCAD.1983.1270039 10.1109/DAC.1982.1585535 10.1007/BF02579150 10.1137/S1052623497331786 10.1109/CCECE.2001.933590 10.1023/A:1014847925683 10.1109/ICCAD.1999.810613 10.1093/oso/9780195100563.001.0001 10.1109/43.673630 10.1145/369691.369711 10.1007/BF01582166 10.1007/BF01759035 10.1145/127601.127678 10.1109/DAC.1978.1585154 |
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| SubjectTerms | Design and construction Design engineering global routing Heuristic Integer programming Integrated circuit fabrication Integrated circuits Linear programming linear relaxation Methods Semiconductor chips Studies Technology application Transistors Very-large-scale integration VLSI layout |
| Title | Integer Linear Programming Models for Global Routing |
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