Enhanced Interpolated-DFT for Synchrophasor Estimation in FPGAs: Theory, Implementation, and Validation of a PMU Prototype

The literature on the subject of synchrophasor estimation (SE) algorithms has discussed the use of interpolated discrete Fourier transform (IpDFT) as an approach capable to find an optimal tradeoff between SE accuracy, response time, and computational complexity. Within this category of algorithms,...

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Veröffentlicht in:	IEEE transactions on instrumentation and measurement Jg. 63; H. 12; S. 2824 - 2836
Hauptverfasser:	Romano, Paolo, Paolone, Mario
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.12.2014 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Accuracy Algorithm design and analysis Algorithms Assessments Categories Compensation Discrete Fourier transform (DFT) Discrete Fourier transforms field programmable gate array (FPGA) Field programmable gate arrays Global Positioning System IEEE standards IEEE Std. C37.118 Instrumentation interpolated discrete Fourier transform (IpDFT) phasor measurement unit (PMU) Phasor measurement units Programmable logic controllers synchrophasor Discrete Fourier transform (DFT) interpolated discrete Fourier transform (IpDFT) field programmable gate array (FPGA) synchrophasor IEEE Std. C37.118 phasor measurement unit (PMU)
ISSN:	0018-9456, 1557-9662
Online-Zugang:	Volltext
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