An efficient crossover architecture for hardware parallel implementation of genetic algorithm

In this article a new architecture for hardware implementation of genetic algorithm in reconfigurable embedded systems is presented. The main idea is based on the efficient use of a genetic algorithm's crossover operator to enhance the speed of algorithm to reach an optimal solution. In this ar...

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Veröffentlicht in:	Neurocomputing (Amsterdam) Jg. 128; S. 316 - 327
Hauptverfasser:	Faraji, Rasoul, Naji, Hamid Reza
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Amsterdam Elsevier B.V 27.03.2014 Elsevier
Schlagworte:	Algorithmics. Computability. Computer arithmetics Algorithms Applied sciences Architecture Architecture (computers) Computer science; control theory; systems Crossover operator Crossovers Exact sciences and technology FPGA Genetic algorithm Genetic algorithms Hardware Operators Optimization Theoretical computing Genetic algorithm FPGA Crossover operator Optimal algorithm Reuse Field programmable gate array Optimization Circuit architecture Boarded computer Optimal solution Problem solving Parallelism Reconfigurable architectures
ISSN:	0925-2312, 1872-8286
Online-Zugang:	Volltext
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