On optimizing system energy of voltage–frequency island based 3-D multi-core SoCs under thermal constraints - Jin, Song; Wang, Yu; Liu, Tongna (Integration (Amsterdam), 2015)
Three dimensional (3-D) multi-core SoC has been recognized as a promising solution for implementing complex applications with lower system energy. Recently, voltage–frequency island (VFI)-based design paradigm was widely adopted for energy optimization. However, the existing work commonly targeted 2-D platform, which cannot handle the exacerbated thermal issues and the increased solution space from 3-D integration. In this paper, we propose an optimization framework targeting VFI-based 3-D multi-core SoCs to minimize system energy meanwhile still meeting task deadline and thermal constraints. Our framework conducts at an earlier design phase in which designers have the freedom to determine the core stacks and map them into the hardware platform. Besides energy-aware task scheduling, we also conduct core stacking and task adjusting to balance the powers across the chip for thermal optimization. Moreover, by treating each core stack as a unity, the complicated problem of core mapping and VFI partitioning in 3-D platform can be simplified as a 2-D one. Experimental results demonstrate that on average our framework can achieve an energy reduction of 15.8% over the prior thermal balancing algorithm [17] (X. Zhou, J. Yang, Y. Xu, et al. Thermal-aware task scheduling for 3D multicore processors, IEEE Trans. Parallel Distrib. Syst. (TPDS), 21(1) (2010), 60–71.). Moreover, on average a reduction of 4.8°C in peak temperature is achieved by our framework, compared with the state-of-the-art energy optimization scheme [8] (U.Y. Ogras, R. Marculescu, P. Choudhary, et al. Voltage–frequency island partitioning for GALS-based networks-on-chip, in: ACM/IEEE Design Automation Conference (DAC), 2007, pp. 110–115.). •We unified consider task scheduling and V/F scaling to minimize computation energy.•Core stacking and task migrating are performed to balance powers across the chip.•We simplify 3-D mapping problem into a 2-D one by treating core stack as a unity.