On optimizing system energy of voltage–frequency island based 3-D multi-core SoCs under thermal constraints
Three dimensional (3-D) multi-core SoC has been recognized as a promising solution for implementing complex applications with lower system energy. Recently, voltage–frequency island (VFI)-based design paradigm was widely adopted for energy optimization. However, the existing work commonly targeted 2...
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| Vydáno v: | Integration (Amsterdam) Ročník 48; s. 36 - 45 |
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01.01.2015
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| ISSN: | 0167-9260, 1872-7522 |
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| Abstract | Three dimensional (3-D) multi-core SoC has been recognized as a promising solution for implementing complex applications with lower system energy. Recently, voltage–frequency island (VFI)-based design paradigm was widely adopted for energy optimization. However, the existing work commonly targeted 2-D platform, which cannot handle the exacerbated thermal issues and the increased solution space from 3-D integration. In this paper, we propose an optimization framework targeting VFI-based 3-D multi-core SoCs to minimize system energy meanwhile still meeting task deadline and thermal constraints. Our framework conducts at an earlier design phase in which designers have the freedom to determine the core stacks and map them into the hardware platform. Besides energy-aware task scheduling, we also conduct core stacking and task adjusting to balance the powers across the chip for thermal optimization. Moreover, by treating each core stack as a unity, the complicated problem of core mapping and VFI partitioning in 3-D platform can be simplified as a 2-D one. Experimental results demonstrate that on average our framework can achieve an energy reduction of 15.8% over the prior thermal balancing algorithm [17] (X. Zhou, J. Yang, Y. Xu, et al. Thermal-aware task scheduling for 3D multicore processors, IEEE Trans. Parallel Distrib. Syst. (TPDS), 21(1) (2010), 60–71.). Moreover, on average a reduction of 4.8°C in peak temperature is achieved by our framework, compared with the state-of-the-art energy optimization scheme [8] (U.Y. Ogras, R. Marculescu, P. Choudhary, et al. Voltage–frequency island partitioning for GALS-based networks-on-chip, in: ACM/IEEE Design Automation Conference (DAC), 2007, pp. 110–115.).
•We unified consider task scheduling and V/F scaling to minimize computation energy.•Core stacking and task migrating are performed to balance powers across the chip.•We simplify 3-D mapping problem into a 2-D one by treating core stack as a unity. |
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| AbstractList | Three dimensional (3-0) multi-core SoC has been recognized as a promising solution for implementing complex applications with lower system energy. Recently, voltage-frequency island (VFI)-based design paradigm was widely adopted for energy optimization. However, the existing work commonly targeted 2-D platform, which cannot handle the exacerbated thermal issues and the increased solution space from 3-D integration. In this paper, we propose an optimization framework targeting VFI-based 3-D multi-core SoCs to minimize system energy meanwhile still meeting task deadline and thermal constraints. Our framework conducts at an earlier design phase in which designers have the freedom to determine the core stacks and map them into the hardware platform. Besides energy-aware task scheduling, we also conduct core stacking and task adjusting to balance the powers across the chip for thermal optimization. Moreover, by treating each core stack as a unity, the complicated problem of core mapping and VFI partitioning in 3-D platform can be simplified as a 2-D one. Experimental results demonstrate that on average our framework can achieve an energy reduction of 15.8% over the prior thermal balancing algorithm [17] (X. Zhou, J. Yang, Y. Xu, et al. Thermal-aware task scheduling for 3D multicore processors, IEEE Trans. Parallel Distrib. Syst. (TPDS), 21(1) (2010), 60-71.). Moreover, on average a reduction of 4.8 [degrees]C in peak temperature is achieved by our framework, compared with the state-of-the-art energy optimization scheme [8] (U.Y. Ogras, R. Marculescu, P. Choudhary, et al. Voltage- frequency island partitioning for GALS-based networks-on-chip, in: ACM/IEEE Design Automation Conference (DAC), 2007, pp. 110-115.). Three dimensional (3-D) multi-core SoC has been recognized as a promising solution for implementing complex applications with lower system energy. Recently, voltage–frequency island (VFI)-based design paradigm was widely adopted for energy optimization. However, the existing work commonly targeted 2-D platform, which cannot handle the exacerbated thermal issues and the increased solution space from 3-D integration. In this paper, we propose an optimization framework targeting VFI-based 3-D multi-core SoCs to minimize system energy meanwhile still meeting task deadline and thermal constraints. Our framework conducts at an earlier design phase in which designers have the freedom to determine the core stacks and map them into the hardware platform. Besides energy-aware task scheduling, we also conduct core stacking and task adjusting to balance the powers across the chip for thermal optimization. Moreover, by treating each core stack as a unity, the complicated problem of core mapping and VFI partitioning in 3-D platform can be simplified as a 2-D one. Experimental results demonstrate that on average our framework can achieve an energy reduction of 15.8% over the prior thermal balancing algorithm [17] (X. Zhou, J. Yang, Y. Xu, et al. Thermal-aware task scheduling for 3D multicore processors, IEEE Trans. Parallel Distrib. Syst. (TPDS), 21(1) (2010), 60–71.). Moreover, on average a reduction of 4.8°C in peak temperature is achieved by our framework, compared with the state-of-the-art energy optimization scheme [8] (U.Y. Ogras, R. Marculescu, P. Choudhary, et al. Voltage–frequency island partitioning for GALS-based networks-on-chip, in: ACM/IEEE Design Automation Conference (DAC), 2007, pp. 110–115.). •We unified consider task scheduling and V/F scaling to minimize computation energy.•Core stacking and task migrating are performed to balance powers across the chip.•We simplify 3-D mapping problem into a 2-D one by treating core stack as a unity. |
| Author | Wang, Yu Jin, Song Liu, Tongna |
| Author_xml | – sequence: 1 givenname: Song surname: Jin fullname: Jin, Song email: jinsong@ncepu.edu.cn – sequence: 2 givenname: Yu surname: Wang fullname: Wang, Yu email: wangyu@ncepu.edu.cn – sequence: 3 givenname: Tongna surname: Liu fullname: Liu, Tongna email: liutongna@ncepu.edu.cn |
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| Cites_doi | 10.1109/TVLSI.2011.2182067 10.1109/JSSC.2010.2079450 10.1109/TCAD.2008.925793 10.1109/CICC.2008.4672173 10.1145/1278480.1278509 10.1145/1391469.1391550 10.1109/DAC.2002.1012617 10.1145/1055137.1055171 10.1049/ip-cdt:20045092 10.1109/ISQED.2006.77 10.1109/DATE.2009.5090885 10.1109/TCAD.2010.2101371 10.1109/TPDS.2009.27 10.1145/1150019.1136497 10.1109/ICCAD.2008.4681584 10.1109/JSSC.2011.2109630 10.1109/ISSCC.2008.4523070 10.1109/TVLSI.2006.884166 10.1109/ISSCC.2007.373608 10.1145/2024724.2024774 10.1109/DATE.2011.5763213 10.1109/DATE.2006.243773 |
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| Keywords | Voltage–frequency island Power balancing Thermal constraint System energy 3-Dimensional SoCs Interconnection network State of the art Partition method Stacking Voltage-frequency island Network architecture Mapping Implementation Optimization Partitioning Three dimensional structure Electric power consumption Minimum energy Globally asynchronous locally synchronous Task scheduling System on a chip Algorithm Energy savings Multicore processor Three dimensional model Integrated circuit Low-power electronics |
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| References | F. Clermidy, F. Darve, D. Dutoit, et al., 3D Embedded multi-core: some perspectives, in: ACM/IEEE Design, Automation and Test in Europe (DATE), 2011, pp. 1327–1332. Hu, Marculescu (bib9) 2005; 152 M.S. Bakir, C. King, D. Sekar, et al., 3D heterogeneous integrated systems: liquid cooling, power delivery, and implementation, in: IEEE Custom Integrated Circuits Conference (CICC), 2008, pp. 663–670. 〉 Available at W. Jang, D. Duo, D. Z. Pan. A voltage–frequency island aware energy optimization framework for networks-on-chip, in: ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2008, pp. 264–269. G.M. Link, N. Vijaykrishnan, Thermal trends in emerging technologies, in: International Symposium on Quality Electronic Design (ISQED), 2006, pp. 8–632. Y. Zhang, S. Hu, Z. Danny, Task scheduling and voltage selection for energy minimization, in: ACM/IEEE Design Automation Conference (DAC), 2002, pp. 183–188. Cheng, Zhang, Han (bib12) 2013; 21 B. Goplen, S. Sapatnekar, Thermal via placement in 3D ICs, in: IEEE International Symposium on Physical Design (ISPD), 2005, pp. 167–174. Kang, Kim, Yoo (bib20) 2010; 30 Zhou, Yang, Xu (bib17) 2010; 21 R. Dick, Embedded System Synthesis Benchmarks Suites (E3S), Available at Sekiguchi, Ono, Kotabe (bib2) 2011; 46 E. Wong, S.K. Lim, 3D floorplanning with thermal vias, in: ACM/IEEE Design, Automation and Test in Europe (DATE), 2006, pp. 1–6. W. Hung, G. M. Link, Y. Xie, et al., Interconnect and thermal-aware floorplanning for 3D microprocessors, in: IEEE International Symposium on Quality Electronic Design (ISQED), 2006, pp. 98–104. F. Li, C. Nicopoulos, T. Richardson, et al., Design and management of 3D chip multiprocessors using network-in-memory, in: ACM/IEEE International Symposium on Computer Architecture (ISCA), 2006, pp. 130–141. B. Shane, E. Bruce, A. John, et al., TILE64 processor: a 64-core SoC with mesh interconnect, in: IEEE International Solid-State Circuits Conference (ISSCC), 2008, pp. 88–598. Howard, Dighe, Vangal (bib6) 2011; 46 S. Borkar, 3D integration for energy efficient system design, in: ACM/IEEE Design Automation Conference (DAC), 2011, pp. 214–219. Sinha, Narendra, Zhou (bib21) 2006; 14 Zhu, Gu, Shang (bib18) 2008; 27 U.Y. Ogras, R. Marculescu, P. Choudhary, et al., Voltage-frequency island partitioning for GALS-based networks-on-chip, in: ACM/IEEE Design Automation Conference (DAC), 2007, pp. 110–115. A.K. Coskun, J.L. Ayala, D. Atienza, et al., Dynamic thermal management in 3D multicore architectures, in: ACM/IEEE Design, Automation and Test in Europe (DATE), 2009, pp. 1410–1415. J. Dorsey, S. Searles, M. Ciraula, et al., An integrated quad-core opteron processor, in: IEEE International Solid-State Circuits Conference (ISSCC), 2007, pp. 102–103. S. Herbert, D. Marculescu. Characterizing chip-multiprocessor variability-tolerance, in: ACM/IEEE Design Automation Conference (DAC), 2008, pp. 313–318. 10.1016/j.vlsi.2014.05.001_bib22 Sekiguchi (10.1016/j.vlsi.2014.05.001_bib2) 2011; 46 10.1016/j.vlsi.2014.05.001_bib8 10.1016/j.vlsi.2014.05.001_bib7 Howard (10.1016/j.vlsi.2014.05.001_bib6) 2011; 46 10.1016/j.vlsi.2014.05.001_bib1 Zhou (10.1016/j.vlsi.2014.05.001_bib17) 2010; 21 10.1016/j.vlsi.2014.05.001_bib4 10.1016/j.vlsi.2014.05.001_bib25 10.1016/j.vlsi.2014.05.001_bib3 10.1016/j.vlsi.2014.05.001_bib23 10.1016/j.vlsi.2014.05.001_bib5 10.1016/j.vlsi.2014.05.001_bib24 10.1016/j.vlsi.2014.05.001_bib10 Cheng (10.1016/j.vlsi.2014.05.001_bib12) 2013; 21 10.1016/j.vlsi.2014.05.001_bib11 Sinha (10.1016/j.vlsi.2014.05.001_bib21) 2006; 14 Zhu (10.1016/j.vlsi.2014.05.001_bib18) 2008; 27 Kang (10.1016/j.vlsi.2014.05.001_bib20) 2010; 30 10.1016/j.vlsi.2014.05.001_bib19 10.1016/j.vlsi.2014.05.001_bib16 10.1016/j.vlsi.2014.05.001_bib14 10.1016/j.vlsi.2014.05.001_bib15 Hu (10.1016/j.vlsi.2014.05.001_bib9) 2005; 152 10.1016/j.vlsi.2014.05.001_bib13 |
| References_xml | – volume: 14 start-page: 1140 year: 2006 end-page: 1146 ident: bib21 article-title: Statistical timing yield optimization by gate sizing publication-title: IEEE Trans. Very Large Scale Integr. Syst. – reference: S. Borkar, 3D integration for energy efficient system design, in: ACM/IEEE Design Automation Conference (DAC), 2011, pp. 214–219. – reference: W. Hung, G. M. Link, Y. Xie, et al., Interconnect and thermal-aware floorplanning for 3D microprocessors, in: IEEE International Symposium on Quality Electronic Design (ISQED), 2006, pp. 98–104. – volume: 30 start-page: 905 year: 2010 end-page: 918 ident: bib20 article-title: Runtime power management of 3-D multi-core architectures under peak power and temperature constraints publication-title: IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. – reference: B. Goplen, S. Sapatnekar, Thermal via placement in 3D ICs, in: IEEE International Symposium on Physical Design (ISPD), 2005, pp. 167–174. – reference: E. Wong, S.K. Lim, 3D floorplanning with thermal vias, in: ACM/IEEE Design, Automation and Test in Europe (DATE), 2006, pp. 1–6. – reference: G.M. Link, N. Vijaykrishnan, Thermal trends in emerging technologies, in: International Symposium on Quality Electronic Design (ISQED), 2006, pp. 8–632. – volume: 152 start-page: 643 year: 2005 end-page: 651 ident: bib9 article-title: Communication and task scheduling of application-specific networks-on-chip publication-title: Comput. Digit. Tech. – reference: F. Clermidy, F. Darve, D. Dutoit, et al., 3D Embedded multi-core: some perspectives, in: ACM/IEEE Design, Automation and Test in Europe (DATE), 2011, pp. 1327–1332. – reference: J. Dorsey, S. Searles, M. Ciraula, et al., An integrated quad-core opteron processor, in: IEEE International Solid-State Circuits Conference (ISSCC), 2007, pp. 102–103. – volume: 46 start-page: 173 year: 2011 end-page: 183 ident: bib6 article-title: A 48-core IA-32 processor in 45 publication-title: IEEE J. Solid-State Circuits – reference: F. Li, C. Nicopoulos, T. Richardson, et al., Design and management of 3D chip multiprocessors using network-in-memory, in: ACM/IEEE International Symposium on Computer Architecture (ISCA), 2006, pp. 130–141. – reference: Y. Zhang, S. Hu, Z. Danny, Task scheduling and voltage selection for energy minimization, in: ACM/IEEE Design Automation Conference (DAC), 2002, pp. 183–188. – reference: M.S. Bakir, C. King, D. Sekar, et al., 3D heterogeneous integrated systems: liquid cooling, power delivery, and implementation, in: IEEE Custom Integrated Circuits Conference (CICC), 2008, pp. 663–670. – volume: 21 start-page: 239 year: 2013 end-page: 249 ident: bib12 article-title: Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs publication-title: IEEE Trans. Very Large Scale Integr. Syst. – reference: R. Dick, Embedded System Synthesis Benchmarks Suites (E3S), Available at: 〈 – reference: W. Jang, D. Duo, D. Z. Pan. A voltage–frequency island aware energy optimization framework for networks-on-chip, in: ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2008, pp. 264–269. – volume: 21 start-page: 60 year: 2010 end-page: 71 ident: bib17 article-title: Thermal-aware task scheduling for 3D multicore processors publication-title: IEEE Trans. Parallel Distrib. Syst. – volume: 46 start-page: 828 year: 2011 end-page: 837 ident: bib2 article-title: 1-Tbyte/s 1-Gbit DRAM architecture using 3-D interconnect for high-throughput computing publication-title: IEEE J. Solid-State Circuits – reference: B. Shane, E. Bruce, A. John, et al., TILE64 processor: a 64-core SoC with mesh interconnect, in: IEEE International Solid-State Circuits Conference (ISSCC), 2008, pp. 88–598. – reference: S. Herbert, D. Marculescu. Characterizing chip-multiprocessor variability-tolerance, in: ACM/IEEE Design Automation Conference (DAC), 2008, pp. 313–318. – reference: 〉 – reference: U.Y. Ogras, R. Marculescu, P. Choudhary, et al., Voltage-frequency island partitioning for GALS-based networks-on-chip, in: ACM/IEEE Design Automation Conference (DAC), 2007, pp. 110–115. – reference: Available at: 〈 – reference: A.K. Coskun, J.L. Ayala, D. Atienza, et al., Dynamic thermal management in 3D multicore architectures, in: ACM/IEEE Design, Automation and Test in Europe (DATE), 2009, pp. 1410–1415. – volume: 27 start-page: 1479 year: 2008 end-page: 1492 ident: bib18 article-title: Three-dimensional chip-multiprocessor run-time thermal management publication-title: IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. – ident: 10.1016/j.vlsi.2014.05.001_bib25 – volume: 21 start-page: 239 issue: 2 year: 2013 ident: 10.1016/j.vlsi.2014.05.001_bib12 article-title: Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs publication-title: IEEE Trans. Very Large Scale Integr. Syst. doi: 10.1109/TVLSI.2011.2182067 – volume: 46 start-page: 173 issue: 1 year: 2011 ident: 10.1016/j.vlsi.2014.05.001_bib6 article-title: A 48-core IA-32 processor in 45nm CMOS using on-die message-passing and DVFS for performance and power scaling publication-title: IEEE J. Solid-State Circuits doi: 10.1109/JSSC.2010.2079450 – volume: 27 start-page: 1479 issue: 8 year: 2008 ident: 10.1016/j.vlsi.2014.05.001_bib18 article-title: Three-dimensional chip-multiprocessor run-time thermal management publication-title: IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. doi: 10.1109/TCAD.2008.925793 – ident: 10.1016/j.vlsi.2014.05.001_bib23 – ident: 10.1016/j.vlsi.2014.05.001_bib15 doi: 10.1109/CICC.2008.4672173 – ident: 10.1016/j.vlsi.2014.05.001_bib8 doi: 10.1145/1278480.1278509 – ident: 10.1016/j.vlsi.2014.05.001_bib4 doi: 10.1145/1391469.1391550 – ident: 10.1016/j.vlsi.2014.05.001_bib10 doi: 10.1109/DAC.2002.1012617 – ident: 10.1016/j.vlsi.2014.05.001_bib13 doi: 10.1145/1055137.1055171 – volume: 152 start-page: 643 issue: 5 year: 2005 ident: 10.1016/j.vlsi.2014.05.001_bib9 article-title: Communication and task scheduling of application-specific networks-on-chip publication-title: Comput. Digit. Tech. doi: 10.1049/ip-cdt:20045092 – ident: 10.1016/j.vlsi.2014.05.001_bib7 doi: 10.1109/ISQED.2006.77 – ident: 10.1016/j.vlsi.2014.05.001_bib16 doi: 10.1109/DATE.2009.5090885 – volume: 30 start-page: 905 issue: 6 year: 2010 ident: 10.1016/j.vlsi.2014.05.001_bib20 article-title: Runtime power management of 3-D multi-core architectures under peak power and temperature constraints publication-title: IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. doi: 10.1109/TCAD.2010.2101371 – volume: 21 start-page: 60 issue: 1 year: 2010 ident: 10.1016/j.vlsi.2014.05.001_bib17 article-title: Thermal-aware task scheduling for 3D multicore processors publication-title: IEEE Trans. Parallel Distrib. Syst. doi: 10.1109/TPDS.2009.27 – ident: 10.1016/j.vlsi.2014.05.001_bib19 doi: 10.1145/1150019.1136497 – ident: 10.1016/j.vlsi.2014.05.001_bib11 doi: 10.1109/ICCAD.2008.4681584 – volume: 46 start-page: 828 issue: 4 year: 2011 ident: 10.1016/j.vlsi.2014.05.001_bib2 article-title: 1-Tbyte/s 1-Gbit DRAM architecture using 3-D interconnect for high-throughput computing publication-title: IEEE J. Solid-State Circuits doi: 10.1109/JSSC.2011.2109630 – ident: 10.1016/j.vlsi.2014.05.001_bib22 doi: 10.1109/ISSCC.2008.4523070 – ident: 10.1016/j.vlsi.2014.05.001_bib24 – volume: 14 start-page: 1140 issue: 10 year: 2006 ident: 10.1016/j.vlsi.2014.05.001_bib21 article-title: Statistical timing yield optimization by gate sizing publication-title: IEEE Trans. Very Large Scale Integr. Syst. doi: 10.1109/TVLSI.2006.884166 – ident: 10.1016/j.vlsi.2014.05.001_bib5 doi: 10.1109/ISSCC.2007.373608 – ident: 10.1016/j.vlsi.2014.05.001_bib1 doi: 10.1145/2024724.2024774 – ident: 10.1016/j.vlsi.2014.05.001_bib3 doi: 10.1109/DATE.2011.5763213 – ident: 10.1016/j.vlsi.2014.05.001_bib14 doi: 10.1109/DATE.2006.243773 |
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| SubjectTerms | 3-Dimensional SoCs Applied sciences Circuit properties Design engineering Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Islands Optimization Partitioning Platforms Power balancing Reduction Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors System energy Task scheduling Thermal constraint Three dimensional Voltage–frequency island |
| Title | On optimizing system energy of voltage–frequency island based 3-D multi-core SoCs under thermal constraints |
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