Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm

The purpose of this communication is to present the modeling of an Artificial Neural Network (ANN) for a differential Complementary Metal Oxide Semiconductor (CMOS) Low-Noise Amplifier (LNA) designed for wireless applications. For satellite transponder applications employing differential LNAs, vario...

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Vydáno v:Sensors (Basel, Switzerland) Ročník 23; číslo 21; s. 8790
Hlavní autoři: Subburaman, Bhuvaneshwari, Thangaraj, Vignesh, Balu, Vadivel, Pandyan, Uma Maheswari, Kulkarni, Jayshri
Médium: Journal Article
Jazyk:angličtina
Vydáno: Basel MDPI AG 28.10.2023
Témata:
Algorithms
ANN
Bayesian regularization
capacitor cross-coupling
CMOS
Complementary metal oxide semiconductors
Design
Designers
differential cascode
Earth stations
Energy conservation
gain boosting
low-noise amplifier
Neural networks
Satellite communications
Simulation methods
Technology application
Transistors
Transponders
Wireless telephone software
ISSN:1424-8220, 1424-8220
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Shrnutí:The purpose of this communication is to present the modeling of an Artificial Neural Network (ANN) for a differential Complementary Metal Oxide Semiconductor (CMOS) Low-Noise Amplifier (LNA) designed for wireless applications. For satellite transponder applications employing differential LNAs, various techniques, such as gain boosting, linearity improvement, and body bias, have been individually documented in the literature. The proposed LNA combines all three of these techniques differentially, aiming to achieve a high gain, a low noise figure, excellent linearity, and reduced power consumption. Under simulation conditions at 5 GHz using Cadence, the proposed LNA demonstrates a high gain (S21) of 29.5 dB and a low noise figure (NF) of 1.2 dB, with a reduced supply voltage of only 0.9 V. Additionally, it exhibits a reflection coefficient (S11) of less than −10 dB, a power dissipation (Pdc) of 19.3 mW, and a third-order input intercept point (IIP3) of 0.2 dBm. The performance results of the proposed LNA, combining all three techniques, outperform those of LNAs employing only two of the above techniques. The proposed LNA is modeled using PatternNet BR, and the simulation results closely align with the results of the developed ANN. In comparison to the Cadence simulation method, the proposed approach also offers accurate circuit solutions.
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ISSN:1424-8220
1424-8220
DOI:10.3390/s23218790