High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and In...

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Vydáno v:	IEEE transactions on computers Ročník 69; číslo 4; s. 534 - 548
Hlavní autoři:	Ueno, Rei, Homma, Naofumi, Morioka, Sumio, Miura, Noriyuki, Matsuda, Kohei, Nagata, Makoto, Bhasin, Shivam, Mathieu, Yves, Graba, Tarik, Danger, Jean-Luc
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York IEEE 01.04.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Institute of Electrical and Electronics Engineers
Témata:	AES Algorithms Computer architecture Computer Arithmetic Computer Science Critical path Cryptography and Security Data paths Delay Delays Digital Libraries Electronics Encryption Energy consumption Engineering Sciences Hardware Hardware Architecture hardware architectures Logic gates Logic synthesis Modeling and Simulation Optimization Optimization techniques Poles and towers Power consumption round-based encryption architecture unified encryption/decryption architecture
ISSN:	0018-9340, 1557-9956
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Abstract	This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.
AbstractList	This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.
Author	Homma, Naofumi Graba, Tarik Ueno, Rei Matsuda, Kohei Mathieu, Yves Morioka, Sumio Nagata, Makoto Bhasin, Shivam Danger, Jean-Luc Miura, Noriyuki
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References	ref35 reyhani-masoleh (ref17) 2018 ref34 ref12 ref36 ref14 ref31 ref30 ref33 ref32 ref10 ref2 ref16 ref19 gueron (ref28) 2016 mcgrew (ref26) 2005 ueno (ref15) 2015 naito (ref6) 2017 maximov (ref18) 2019 canright (ref24) 0 ref25 ref20 ref21 morioka (ref11) 2002 ueno (ref7) 2016 lutz (ref1) 2002 ref27 ref29 ref8 nogami (ref13) 2010 ref9 ref4 ref3 ref5 (ref23) 0 (ref22) 2016
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SubjectTerms	AES Algorithms Computer architecture Computer Arithmetic Computer Science Critical path Cryptography and Security Data paths Delay Delays Digital Libraries Electronics Encryption Energy consumption Engineering Sciences Hardware Hardware Architecture hardware architectures Logic gates Logic synthesis Modeling and Simulation Optimization Optimization techniques Poles and towers Power consumption round-based encryption architecture unified encryption/decryption architecture
Title	High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
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