APA (7th ed.) Citation

Ueno, R., Homma, N., Morioka, S., Miura, N., Matsuda, K., Nagata, M., . . . Danger, J. (2020). High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE transactions on computers, 69(4), 534-548. https://doi.org/10.1109/TC.2019.2957355

Chicago Style (17th ed.) Citation

Ueno, Rei, et al. "High Throughput/Gate AES Hardware Architectures Based on Datapath Compression." IEEE Transactions on Computers 69, no. 4 (2020): 534-548. https://doi.org/10.1109/TC.2019.2957355.

MLA (9th ed.) Citation

Ueno, Rei, et al. "High Throughput/Gate AES Hardware Architectures Based on Datapath Compression." IEEE Transactions on Computers, vol. 69, no. 4, 2020, pp. 534-548, https://doi.org/10.1109/TC.2019.2957355.