All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition
This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not requi...
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| Published in: | IEEE transactions on circuits and systems. II, Express briefs Vol. 63; no. 1; pp. 99 - 103 |
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| Main Authors: | , , , , , , |
| Format: | Journal Article |
| Language: | English |
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New York
IEEE
01.01.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Institute of Electrical and Electronics Engineers |
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| ISSN: | 1549-7747, 1558-3791 |
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| Abstract | This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at a very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using a 28-nm fully depleted Silicon on insulator (FD-SOI) CMOS technology for the 11-b 60-dB SNR TIADC clocked at 2.7 GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05 mm 2 and dissipates the total power of 41 mW. |
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| AbstractList | This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at a very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using a 28-nm fully depleted Silicon on insulator (FD-SOI) CMOS technology for the 11-b 60-dB SNR TIADC clocked at 2.7 GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05 mm2 and dissipates the total power of 41 mW. This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at a very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using a 28-nm fully depleted Silicon on insulator (FD-SOI) CMOS technology for the 11-b 60-dB SNR TIADC clocked at 2.7 GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05 mm 2 and dissipates the total power of 41 mW. This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at a very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using a 28-nm fully depleted Silicon on insulator (FD-SOI) CMOS technology for the 11-b 60-dB SNR TIADC clocked at 2.7 GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05 mm super(2) and dissipates the total power of 41 mW. |
| Author | Graba, Tarik Duc Minh Nguyen Jabbour, Chadi Desgreys, Patricia Han Le Duc Jamin, Olivier Van Tam Nguyen |
| Author_xml | – sequence: 1 surname: Han Le Duc fullname: Han Le Duc email: han.le-duc@telecom-paristech.fr organization: Dept. of Comelec, Inst. Mines-Telecom, Paris, France – sequence: 2 surname: Duc Minh Nguyen fullname: Duc Minh Nguyen organization: Dept. of Comelec, Inst. Mines-Telecom, Paris, France – sequence: 3 givenname: Chadi surname: Jabbour fullname: Jabbour, Chadi organization: Nokia Technol., Berkeley, CA, USA – sequence: 4 givenname: Tarik surname: Graba fullname: Graba, Tarik organization: Dept. of Comelec, Inst. Mines-Telecom, Paris, France – sequence: 5 givenname: Patricia surname: Desgreys fullname: Desgreys, Patricia organization: Dept. of Comelec, Inst. Mines-Telecom, Paris, France – sequence: 6 givenname: Olivier surname: Jamin fullname: Jamin, Olivier organization: NXP Semicond., Caen, France – sequence: 7 surname: Van Tam Nguyen fullname: Van Tam Nguyen organization: Dept. of Comelec, Inst. Mines-Telecom, Paris, France |
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| Keywords | timing skew calibration polyphase filtering undersampling time-interleaved analog-to-digital converters (TIADCs) Field-programmable gate array (FPGA)/application-specific-integrated-circuit (ASIC) implementation |
| Language | English |
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| SubjectTerms | Algorithms Calibration Circuits Convergence Depletion Digital circuits Dissipation Electronics Engineering Sciences Finite impulse response filters FPGA/ASIC implementation Niobium polyphase filtering Sampling Time measurements Time-frequency analysis Timing Timing skews calibration Undersampling TIADCs |
| Title | All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition |
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