A fault-tolerant last level cache for CMPs operating at ultra-low voltage

Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent with a hard fault. Block disabling is a micro-architectural technique that...

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Bibliographic Details
Published in:	Journal of parallel and distributed computing Vol. 125; pp. 31 - 44
Main Authors:	Ferrerón, Alexandra, Alastruey-Benedé, Jesús, Suárez Gracia, Darío, Monreal Arnal, Teresa, Ibáñez Marín, Pablo, Viñals Yúfera, Víctor
Format:	Journal Article Publication
Language:	English
Published:	Elsevier Inc 01.03.2019 Elsevier
Subjects:	Arquitectura de computadors Cache management Fault-tolerance Fault-tolerant computing Informàtica Multiprogramació (Ordinadors electrònics) Multiprogramming (Electronic computers) Near-threshold voltage On-chip caches SRAM reliability Tolerància als errors (Informàtica) Àrees temàtiques de la UPC SRAM reliability Near-threshold voltage Cache management Fault-tolerance On-chip caches
ISSN:	0743-7315, 1096-0848
Online Access:	Get full text
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