A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond...

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Bibliographic Details
Published in:	IEEE transactions on circuits and systems. II, Express briefs Vol. 56; no. 11; pp. 865 - 869
Main Authors:	Xueqiang, Wang, Liyang, Pan, Dong, Wu, Chaohong, Hu, Runde, Zhou
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.11.2009 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Chaos Circuits Decoders Decoding Delay Error correction Error correction codes Error-correcting code (ECC) fast-decoding algorithm Flash memory Flash memory (computers) Galois fields High speed Iterative algorithms Iterative decoding Mathematical analysis Microelectronics multilevel-cell (MLC) nor flash memories Transformations two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder
ISSN:	1549-7747, 1558-3791
Online Access:	Get full text
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